BOM-DAT/Ferrite-Bead-dat/Ferrite-Bead-dat.md
... ...
@@ -34,11 +34,15 @@ Applications:
34 34
35 35
### 21PG331SN1D
36 36
37
-### more
37
+## more
38 38
39 39
- BLM18EG601SN1D
40 40
- BLM18SG331TZ1D
41 41
42
+MH1608-101Y == 100 Ohms @ 100 MHz 1 Power, Signal Line Ferrite Bead 0603 (1608 Metric) 3A 40mOhm
43
+
44
+
45
+
42 46
## ref
43 47
44 48
- [[BOM-dat]]
... ...
\ No newline at end of file
BOM-DAT/TVS-dat/TVS-dat.md
... ...
@@ -27,6 +27,14 @@ Conclusion:
27 27
28 28
29 29
30
+
31
+## more TVS
32
+
33
+STS321070U162 == Eaton TVS diode ESD supp. SOD-323 size, 7 op. voltage, 165 pF, 30 kV, Unidirectional
34
+
35
+
36
+
37
+
30 38
## ref
31 39
32 40
- [[TVS]]
... ...
\ No newline at end of file
Chip-dat/chip-dat.md
... ...
@@ -50,11 +50,10 @@ from a to z
50 50
51 51
- [[PIC-dat]]
52 52
53
-[[TI-dat]] - [[ti-motor-dat]] - [[ti-audio-dat]] - [[ti-logic-dat]] - [[NE555-dat]]
54 53
55 54
[[realtek-dat]] - [[RTL8211-dat]]
56 55
57
-[[richtek-dat]]
56
+
58 57
59 58
- [[raspberry-pi-dat]]
60 59
... ...
@@ -64,19 +63,29 @@ from a to z
64 63
65 64
- [[semtech-dat]] - [[SX1262-dat]] - [[sx1278-dat]] - [[LLCC68-dat]]
66 65
67
-- [[FTDI-dat]]
66
+- [[toshiba-dat]]
67
+
68
+- [[TI-dat]] - [[ti-motor-dat]] - [[ti-audio-dat]] - [[ti-logic-dat]] - [[NE555-dat]]
68 69
69 70
70 71
72
+- [[FTDI-dat]]
73
+
74
+
71 75
- [[InvenSense-dat]]
72 76
73 77
- [[novosense-dat]]
74 78
75 79
- [[ever-analog-dat]]
76 80
77
-## function
78 81
79
-- [[comparator-dat]]
82
+
83
+
84
+
85
+
86
+## relevant
87
+
88
+- [[circuits-dat]]
80 89
81 90
## ref
82 91
Chip-dat/toshiba-dat/toshiba-dat.md
... ...
@@ -4,4 +4,16 @@
4 4
5 5
- [[TB67H470-dat]]
6 6
7
-- [[TB6612-dat]]
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\ No newline at end of file
0
+- [[TB6612-dat]]
1
+
2
+
3
+TLP5214 == Photocouplers GaAℓAs Infrared LED & Photo IC
4
+
5
+- Isolated IGBT/Power MOSFET gate drive
6
+- AC and brushless DC motor drives
7
+- Industrial Inverters and Uninterruptible Power Supply (UPS)
8
+
9
+
10
+## ref
11
+
12
+- [[chip-dat]]
... ...
\ No newline at end of file
Circuits-dat/PPL-dat/PPL-dat.md
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@@ -0,0 +1,55 @@
1
+
2
+# PPL-dat
3
+
4
+## chip
5
+
6
+- CD4046B == CMOS Micropower Phase-Locked Loop (PLL) with VCO
7
+
8
+
9
+## info
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+
11
+A **PLL** is a control system that **locks the phase of its output signal to the phase of an input signal**, commonly used in frequency synthesis, modulation, demodulation, and timing applications.
12
+
13
+
14
+## 2. Key Features
15
+- **CMOS technology** → low power consumption, high noise immunity
16
+- **Micropower** → suitable for battery-powered circuits
17
+- **Phase Comparator** → detects phase differences between input and feedback
18
+- **Voltage-Controlled Oscillator (VCO)** → generates an output frequency that is controlled by an input voltage
19
+- **Lock Detection** → indicates when PLL is phase-locked
20
+
21
+
22
+## 3. Block Diagram
23
+
24
+
25
+ ┌────────────┐
26
+ IN ──►│ Phase Comp │─────► Charge Pump / Filter ──► VCO ──► OUT
27
+ └────────────┘
28
+ ▲
29
+ │
30
+ └────────── Feedback
31
+
32
+
33
+## 4. Internal Components
34
+1. **Phase Comparator I & II**
35
+ - Compares input signal phase with VCO feedback
36
+ - Generates an error signal proportional to the phase difference
37
+
38
+2. **Voltage-Controlled Oscillator (VCO)**
39
+ - Produces output frequency based on control voltage
40
+ - Frequency range can be set by external resistors and capacitors
41
+
42
+3. **Low-Pass Filter (External)**
43
+ - Smooths the phase comparator output to control VCO
44
+
45
+4. **Lock Detector**
46
+ - Indicates when input and VCO are phase-synchronized
47
+
48
+---
49
+
50
+## 5. Applications
51
+- Frequency synthesis (e.g., FM/AM transmitters and receivers)
52
+- Frequency demodulation
53
+- Clock generation and synchronization
54
+- Tone decoding
55
+- Phase modulation/demodulation
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\ No newline at end of file
Circuits-dat/circuits-dat.md
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@@ -16,10 +16,27 @@
16 16
17 17
- [[DC-blocking-dat]] - [[AC-blocking-dat]]
18 18
19
-- [[logic-gate-dat]] - [[buffer-dat]]
19
+
20 20
21 21
- [[switching-dat]] - [[switch-dat]]
22 22
23
+
24
+- [[comparator-dat]]
25
+
26
+- [[PPL-dat]]
27
+
28
+- [[counter-dat]]
29
+
30
+- [[PWM-dat]]
31
+
32
+
33
+
34
+- [[logic-dat]] - [[logic-gate-dat]] - [[buffer-dat]]
35
+
36
+
37
+
38
+
39
+
23 40
## repo
24 41
25 42
- https://github.com/Edragon/logic-shifter
Circuits-dat/comparator-dat/comparator-dat.md
... ...
@@ -1,6 +1,11 @@
1 1
2 2
# comparator-dat
3 3
4
+
5
+
6
+LM111, LM211, LM311 Differential Comparators
7
+
8
+
4 9
- [[LM393-dat]] - [[UA741-dat]]
5 10
6 11
Circuits-dat/counter-dat/counter-dat.md
... ...
@@ -0,0 +1,10 @@
1
+
2
+# counter-dat
3
+
4
+CD4018B == CMOS Presettable Divide-By-N Counter
5
+
6
+
7
+
8
+## ref
9
+
10
+- [[circuits-dat]]
... ...
\ No newline at end of file
Circuits-dat/flip-flop-dat/flip-flop-dat.md
... ...
@@ -0,0 +1,63 @@
1
+
2
+# flip-flop-dat
3
+
4
+## chip
5
+
6
+- [[TI-dat]] - [[CD4013B-dat]] == CD4013B CMOS Dual D-Type Flip-Flop
7
+
8
+## info
9
+
10
+A **flip-flop** is a **basic digital storage circuit** used to store **1 bit of binary information (0 or 1)**.
11
+It is a fundamental building block for **registers, counters, and state machines** in digital systems.
12
+
13
+---
14
+
15
+## 2. Functions
16
+- **Data Storage**: Remembers the current input state until the next trigger signal arrives.
17
+- **Synchronous Control**: Most flip-flops sample and store data based on a **clock signal (CLK)**.
18
+- **State Retention**: Maintains its current output even if the input disappears until the next trigger.
19
+
20
+---
21
+
22
+## 3. Basic Types
23
+
24
+1. **SR Flip-Flop (Set-Reset)**
25
+ - Inputs: S (Set), R (Reset)
26
+ - Behavior:
27
+ - S=1, R=0 → Q=1
28
+ - S=0, R=1 → Q=0
29
+ - S=0, R=0 → Keep current state
30
+ - S=1, R=1 → Forbidden/invalid state
31
+
32
+2. **D Flip-Flop (Data/Delay)**
33
+ - Inputs: D (Data), CLK (Clock)
34
+ - Behavior:
35
+ - Samples D on clock rising edge and holds Q until the next clock edge.
36
+
37
+3. **JK Flip-Flop**
38
+ - Resolves the forbidden state of SR flip-flop.
39
+ - J=K=1 → Toggle current state Q
40
+
41
+4. **T Flip-Flop (Toggle)**
42
+ - Toggles its state on each clock pulse.
43
+ - Commonly used in counters.
44
+
45
+---
46
+
47
+## 4. Working Principle
48
+
49
+ Clock ↑ ──► Flip-flop samples input D
50
+ D = 1 ──► Q = 1
51
+ D = 0 ──► Q = 0
52
+ Q holds the value until the next clock edge
53
+
54
+## 5. Applications
55
+
56
+- Registers
57
+- Counters
58
+- Finite State Machines (FSM)
59
+- Data synchronization/delay
60
+
61
+## ref
62
+
63
+- [[circuits-dat]]
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\ No newline at end of file
Tech-dat/PWM-dat/PWM-dat.md
... ...
@@ -29,6 +29,16 @@
29 29
https://www.arduino.cc/en/Tutorial/BuiltInExamples/Fade
30 30
*/
31 31
32
+
33
+
34
+## drive chip
35
+
36
+- TL494 == Pulse-Width-Modulation Control Circuits
37
+
38
+
39
+
40
+
41
+
32 42
## ref
33 43
34 44
- [[tech-dat]]
... ...
\ No newline at end of file
Tech-dat/amplifier-dat/amplifier-dat.md
... ...
@@ -109,6 +109,9 @@ Active Low Pass filter with Amplification
109 109
110 110
- TL071CP
111 111
112
+- TL082 == Wide Bandwidth Dual JFET Input Operational Amplifier
113
+
114
+
112 115
113 116
## ref
114 117
Tech-dat/logic-dat/logic-gate-dat/logic-gate-dat.md
... ...
@@ -68,6 +68,11 @@ in positive logic.
68 68
| Positive-AND gate | Same thing — "positive" means using standard logic levels (high = 1) |
69 69
| Negative logic | Less common, where high voltage = logic 0 |
70 70
71
+## more gate chips
72
+
73
+- CDx4HC11 == Triple 3-Input AND Gates
74
+
75
+- CD4001B, CD4002B, CD4025B == CMOS NOR Gates
71 76
72 77
73 78
## ref
power-dat/DC-dat/LDO-dat/LDO-dat.md
... ...
@@ -92,6 +92,9 @@ MC7824BD2TG == Linear Voltage Regulators 24V 1A Positive
92 92
93 93
Nisshinbo Micro Devices Inc. **NJM78L05UA-TE2** == Fixed Positive Standard Regulator, 5VBIPolar, PSSO3, MINI, PLASTIC, SOT-89, 3 PIN
94 94
95
+MIC5365 == High Performance Single 150mA LDO
96
+
97
+MIC5528 == Single High Performance 500mA LDO w/ Auto Discharge & Internal Enable Pulldown
95 98
96 99
97 100
## ref