ef81c6d12c621548bc9e273754172219c4e2a34e
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Board-dat/DOD/DODS044-dat/DODS044-dat.md
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5 | 5 | https://www.electrodragon.com/product/altera-cpld-epm240-epm570-dev-board/ |
6 | 6 | |
7 | 7 | |
8 | +## Board Look |
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9 | + |
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10 | +![](2024-11-04-17-52-53.png) |
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11 | + |
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12 | +## EPM570 vs. EPM240 |
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13 | + |
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14 | +PCB supports two chips at the same time: EPM240T100C5N and EPM570T100C5N. |
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15 | + |
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16 | +The two are the same in terms of package, but have 4 different pin definitions: |
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17 | +- PIN37, 39, 88, and 90 of EPM240T100C5N are used as IO. |
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18 | +- PIN37 and 90 of EPM570T100C5N must be connected to GND; PIN39 and 88 must be connected to 3.3V. |
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19 | + |
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20 | +Therefore, if the board you purchased is EPM570T100C5N, the board should have 4 short-circuit jumpers, which must be brought in and cannot be removed, otherwise the circuit will not work properly. |
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21 | + |
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22 | + |
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23 | +## power supply |
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24 | + |
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25 | +![](2024-11-04-17-51-02.png) |
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26 | + |
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27 | +The development board is powered by 5V input. We recommend purchasing a standard 5V/2A power supply from our store, with positive inside and negative outside. |
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28 | + |
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29 | +If you use other power supplies, please make sure the output voltage is 5V to avoid damage to the development board due to voltage differences! |
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30 | + |
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31 | + |
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32 | +## Clock |
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33 | + |
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34 | +- (i) CLK0 is used as the system working clock and is directly connected to a 50MHz crystal oscillator; |
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35 | +- (ii) CLK1 is used as a reserved clock; |
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36 | +- (iii) CKL2 and CLK3 are user input pins, which are brought out with pin headers for user use; |
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37 | +- PIN44 occupied by reset can be used not only for reset but also as an independent button. Please use it flexibly. |
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38 | + |
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39 | +## schematic |
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40 | + |
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41 | +- please reply to the order email to get |
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42 | + |
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43 | + |
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8 | 44 | ## ref |
9 | 45 | |
10 | -- [[EPM570-dat]] - [[DODS044]] |
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46 | +- [[EPM570-dat]] - [[DODS044]] - [[DODS044-dat]] |
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11 | 47 | |
12 | 48 | - [[CPLD-dat]] - [[FPGA-dat]] |
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Chip-dat/altera-dat/EPM570-dat/EPM570-dat.md
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1 | + |
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2 | +# EPM570-dat |
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3 | + |
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4 | + |
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5 | +## ref |
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6 | + |
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7 | +- [[EPM570-dat]] - [[DODS044]] - [[DODS044-dat]] |
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8 | + |
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9 | +- [[CPLD-dat]] - [[FPGA-dat]] |
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Tech-dat/MCU-dat/CPLD-dat/cpld-dat.md
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5 | 5 | |
6 | 6 | - [[DODS044-dat]] - [[DODS042-dat]] |
7 | 7 | |
8 | +https://www.electrodragon.com/w/Altera_CPLD_EPM240_EPM570_Dev._Board |
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8 | 9 | |
9 | 10 | |
10 | 11 | ## programmer |
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13 | 14 | |
14 | 15 | - [[DPR1077-dat]] |
15 | 16 | |
17 | +### JTAG |
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18 | + |
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19 | +![](2024-11-04-17-50-07.png) |
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16 | 20 | |
21 | +do NOT plug the JTAG cable while powering UP !! |
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17 | 22 | |
18 | 23 | ## software |
19 | 24 | |
... | ... | @@ -39,28 +44,20 @@ XILINX - CPLD |
39 | 44 | |
40 | 45 | ### Intel / Altera |
41 | 46 | |
47 | +MAXII is the lowest power, lowest cost CPLD ever - quote from altera website |
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48 | + |
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42 | 49 | * EPM240 |
43 | 50 | * EPM570 |
44 | 51 | |
45 | 52 | https://www.altera.com/products/cpld/max-series/max-ii/overview.html |
46 | 53 | |
47 | -#### MAX II |
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48 | - |
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49 | -* EPM240 - 8 |
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50 | -* EPM570 |
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54 | +![](2024-11-04-17-54-35.png) |
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51 | 55 | |
52 | 56 | * EPM3032 |
53 | 57 | * EPM3064 |
54 | 58 | |
55 | 59 | |
56 | -### MAX II |
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57 | -https://www.altera.com/products/cpld/max-series/max-ii/overview.html |
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58 | - |
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59 | - |
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60 | -https://www.electrodragon.com/w/Altera_CPLD_EPM240_EPM570_Dev._Board |
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61 | - |
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62 | - |
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63 | -### Altera |
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60 | +### MAX10 |
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64 | 61 | |
65 | 62 | * max1010m02 |
66 | 63 |