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-# PCB-Castellated-Holes-dat
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+# PCB Castellated Holes
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-With the rapid development of electronic technology, electronic products are moving towards miniaturization, portability, multifunctionality, high integration, and high reliability.
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+## Overview
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-Printed circuit boards (PCBs), as the support and connectors for electronic components, often require the integration of core small carrier boards and PCBs in applications.
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+Castellated holes, also called half-holes or plated half-holes, are metallized holes cut along the board edge. They are widely used on small module boards such as Bluetooth, NB-IoT, and other IoT daughter boards so the module can be soldered directly onto a main PCB.
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-For example, Bluetooth/NB-IoT modules for the Internet of Things (IoT) can be soldered onto PCBs like chips. These small carrier boards are characterized by their small size and rows of metallized half-holes along their edges.
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-
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-These metallized half-holes are used to solder the PCB to the motherboard and the component leads; this PCB manufacturing process is known in the industry as the half-hole process.
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+这类 PCB 在板边会有一整排半金属化孔，常用于小型载板、核心板或子板。通过这些半孔，可以将模块像贴片器件一样焊接到母板上。
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![](2026-04-18-15-01-56.png)
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![](2026-04-18-15-02-20.png)
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-这类板边有整排半金属化孔的 PCB ，其特点是孔径比较小，大多用于载板上，作为一个母板的子板，通过这些半金属化孔与母板以及元器件的引脚焊接到一起。
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-
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-
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-
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-■ 半孔的难点
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-
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-如何控制好板边半金属化孔成型后的产品质量，如孔壁铜刺脱落翘起、残留一直是加工过程中的一个难题。如果这些半金属化孔内残留有铜刺，在插件厂家进行焊接的时候，将导致焊脚不牢、虚焊，严重的会造成两引脚之间桥接短路。
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+---
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+## Process Challenges
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+The main difficulty of castellated-hole manufacturing is maintaining good copper quality after the board edge is routed.
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-常规的生产中，半孔是先钻个圆孔再沉铜，难点是去掉另一半的孔的同时，需要保证剩下的一半孔壁有铜存在且不脱落不翘起。
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+Common problems include:
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+- copper burrs lifting from the hole wall
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+- copper residue remaining in the half-hole
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+- poor soldering strength
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+- false soldering or short circuits between adjacent pins
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-无论是钻加工还是铣加工，其SPINDLE（主轴）的旋转方向都是顺时针的。当刀具加工到A点的时候，由于A点的孔壁金属化层与基材层紧密相连，因此附着在孔壁上的金属化层具有支撑，可防止金属化层在加工时的延伸以及金属化层与孔壁的分离，保证此处加工后的不会产生铜刺翘起、残留; 而当刀具加工到B点的时候，由于附着在孔壁上的铜没有任何附着力支撑，刀具向前运转时，受外力影响孔内金属化层就会随刀具旋转方向卷曲，产生铜刺翘起、残留，这些都将直接影响客户的安装及使用。
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+In a standard process, the hole is drilled first and then copper plated. The challenge is to remove half of the hole while still keeping the remaining copper wall intact, conductive, and firmly attached.
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+During drilling or milling, the spindle rotates clockwise. At different cutting positions, the copper support condition changes. If the unsupported copper is pulled by the cutting tool, it may curl up, leave burrs, or remain as residue inside the hole, which directly affects assembly and reliability.
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+To solve this, the board is processed with a dedicated castellated-hole flow. After drilling and copper plating, secondary drilling or CNC routing is used to form the final board outline while preserving one half of the metallized hole.
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-为实现上述目的，我们经过前期多次探索试验，已熟练掌握半孔工艺制作。一次钻孔经沉铜孔化后再采用二钻/锣板外形工艺，最终保留金属化孔（槽）的一半。简单的说就是板边金属化孔切一半，同时保证孔壁铜面完整导通，以便客户焊接使用，目前半孔工艺已经是很成熟的工艺！
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+---
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+## Why Castellated Holes Cost More
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+Castellated holes require a special production flow.
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-半孔板要增加费用的原因：半孔是一种特殊工艺流程，为了保证孔内有铜，必须得工序做到一半的时候先锣边，而且一般的半孔板非常小，所以半孔板一般费用比较高，非常规设计得非常规价格。有需要做半孔的，请在下单平台选择半孔工艺。
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+- extra routing steps are needed during fabrication
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+- the copper inside the hole must remain complete after edge cutting
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+- many castellated boards are very small, which increases handling difficulty
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-## 非半孔工艺的隐患：
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+For this reason, castellated-hole boards usually cost more than standard PCB designs.
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-若不做半孔工艺，可能会有以下几个隐患：
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+---
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-1）孔内铜面卷起
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+## Risks Without the Proper Half-Hole Process
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-2）孔内没有铜皮
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+If a normal process is used instead of a real castellated-hole process, the following issues may occur:
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-3）孔边残留铜面卷起形成披峰，严重时会搭附在相邻焊盘引起短路
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+1. copper in the hole may curl up
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+2. the hole wall may have no copper left
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+3. copper burrs may remain on the edge and cause solder bridging or shorts
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![](2026-04-18-15-03-59.png)
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-## 半孔的设计
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+---
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-A 半孔孔边到板边距离≥1MM
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+## Design Guidelines
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-B 半孔直径大小≥0.5MM
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+| Item | Recommendation |
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+| --- | --- |
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+| Distance from half-hole edge to board edge | ≥ 1.0 mm |
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+| Half-hole diameter | ≥ 0.5 mm |
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+| Distance from hole edge to adjacent hole edge | ≥ 0.5 mm |
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+| Single-side annular ring | Recommended ≥ 0.25 mm, limit 0.18 mm |
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-C 半孔孔边到孔边≥0.5MM
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-
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-D 半孔单边焊环0.25mm(极限0.18mm)以上，小于此参数工程会适当优化，对于半孔间焊盘间隙有要求的请下单时说明并确认生产稿
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+> If the annular ring or pad spacing is smaller than the recommended value, engineering optimization may be required. If your design has special spacing requirements, please confirm them before production.
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![](2026-04-18-15-05-00.png)
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-可以制作圆形或椭圆形半孔（其焊盘形状可以为圆形或方形），但需要留意半孔在设计中尽量焊盘向板框线内部（挂铜）区域放。
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+Round or oval castellated holes can be manufactured, and the pad shape may be round or square. For better manufacturability, place the pad as much as possible toward the inner side of the board frame area.
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-## penalization
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+---
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-半孔板单板尺寸长宽≥10MM（拼板的也需要满足此尺寸），跟常规的板一样，半孔板也可以采用V割和邮票孔拼板法。
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+## Panelization Notes
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-需要强调一点：半孔边不可做V割成形（因为V割会拉铜丝，造成孔内无铜），一定要锣空（CNC）成形。
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+For castellated-hole boards:
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+- single board size should be at least 10 mm × 10 mm
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+- panelized boards should also meet the same minimum size
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+- stamp-hole panelization can be used
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+- CNC routing is required on the castellated edge
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-![](2026-04-18-15-06-25.png)
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+### Important Restriction
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+Do not use V-cut on the castellated-hole edge. V-cut may pull copper from the hole wall and lead to incomplete plating. Use CNC routing instead.
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-Stamp holes panelization
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+![](2026-04-18-15-06-25.png)
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+
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+### Stamp-Hole Panelization
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![](2026-04-18-15-07-40.png)
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+### Full Castellated-Hole Panelization
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+
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+![](2026-04-18-15-11-00.png)
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fab-dat/fab-PCB-dat/PCB-service-dat/PCB-service-dat.md
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## tech
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-- [[PCB-service-dat]] - [[PCB-standards-dat]] - [[PCB-gold-fingers-dat]] - [[PCB-Castellated-Holes-dat]]
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+- [[PCB-service-dat]] - [[PCB-standards-dat]] - [[PCB-gold-fingers-dat]] - [[PCB-Castellated-Holes-dat]] - [[PCB-penalization-dat]] - [[many-penalization-examples-dat]] - [[solder-mask-dat]]
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## extra cost list
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| Board Thickness | 1.6mm | 0.8mm, 1.0mm, 1.2mm | +3 | 0.6mm, 2.0mm | +10 |
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| Board Quantity | 10PCs | 10PCs | +10 | | |
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| Board Material | FR-4 | Copper, Alumimium, FPC Soft | | | |
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-| Board Layer | 2 | | | | |
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+| Board Layer | 2 | 4 | +10 | 8~16 layers | |
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| Lead Time | Default Color GREEN: 1-3 Days | Default Other Color == 4-6 days | | Express within 50 hours. | +10 |
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| Board Color | Green | White, Black, Red, Blue, Yellow | | | |
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| Board Size L x W in CM | Within 10x10 cm^2 | within 10x15 cm^2 | +22 | | |
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| Penalization | No Penalization | v-cut or stamp holes, etc | +10 | | |
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| [[PCB-Castellated-Holes-dat]] | x | With Castellated Holes | +30 | |
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-
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+| [[PCB-vias-dat]] | 0.3mm | 0.25 ~ 0.15 mm | + 60 |
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## ref
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fab-dat/fab-PCB-dat/PCB-vias-dat/PCB-vias-dat.md
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+
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+# PCB-vias-dat
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+
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+default minimal vias == 0.3 mm
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\ No newline at end of file
fab-dat/fab-PCB-dat/solder-mask-dat/2026-04-18-15-18-24.png
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fab-dat/fab-PCB-dat/solder-mask-dat/solder-mask-dat.md
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+
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+
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+# Solder Mask
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+
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+## Via Covering Types
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+
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+![](2026-04-18-15-18-24.png)
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+
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+This page summarizes common via covering and plugging types used in PCB manufacturing.
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+
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+---
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+
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+## 1. Tented Via
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+
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+**Definition:**
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+After the via wall is copper plated, solder mask ink covers the via pad. Some ink may flow into the hole. No solder should remain on the pad surface. Slight yellowing around the via opening is considered normal.
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+
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+**Inspection standard:**
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+The via pad should not take solder during wave soldering or manual soldering.
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+
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+---
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+
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+## 2. Via Opening
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+
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+**Definition:**
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+After copper plating, the via pad is left exposed instead of being covered by solder mask. The exposed copper surface is then finished with HASL or ENIG. If HASL is used, some solder may remain inside the hole.
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+
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+**Inspection standard:**
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+The via pad should solder normally during wave soldering or manual soldering.
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+
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+---
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+
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+## 3. Via Plugging with Solder Mask Ink
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+
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+**Definition:**
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+After copper plating, solder mask ink is filled into the via, and then the full board is coated with solder mask. The via pad surface is also covered with ink. The plugging rate can reach more than 98%.
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+
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+**Inspection standard:**
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+- yellow opening rate on via pads: < 5%
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+- pad surface should not take solder
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+- light-blocking rate of plugged vias: ≥ 95%
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+
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+---
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+
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+## 4. Resin Plugged Via
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+
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+**Definition:**
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+After copper plating, the via is filled with epoxy resin and then copper plated flat on the surface. The plated area and via pad are then covered with solder mask, which gives better protection and makes the hole less visible from the surface.
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+
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+**Applicable via size:**
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+$0.15 \, \text{mm} \text{ to } 0.55 \, \text{mm}$
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+
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+**Inspection standard:**
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+- no light transmission
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+- covered pads should print ink normally
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+- opened pads should support normal HASL or ENIG finishing
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+
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+---
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+
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+## 5. Copper Paste Filled Via
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+
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+**Definition:**
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+This process uses high-thermal-conductivity copper paste to fill the via after copper plating, followed by surface copper plating and solder mask covering. It protects the via and also improves current carrying and heat transfer performance.
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+
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+**Thermal conductivity:**
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+$8\,W/(m\cdot K)$
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+
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+**Applicable via size:**
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+$0.15 \, \text{mm} \text{ to } 0.55 \, \text{mm}$
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+
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+**Inspection standard:**
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+- no light transmission
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+- covered pads should print ink normally
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+- opened pads should support normal HASL or ENIG finishing
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+