f133

+

+- [[mini-PCIE-dat]]

+

+

+## PCIE 1x

+

+A PCIe x1 slot is a type of expansion slot on a computer motherboard, primarily designed for low-bandwidth devices. It has a single PCIe lane, offering the lowest data transfer rate among different PCIe slot types. Despite its limitations, it's useful for various low-power peripheral cards.

+

+

+

+18 *2 = 36 pins

+

+

+

+

+

+## ref

+

+- [[interface-dat]]

+

+

+

+

+

+

+

+- 52-pin

+

+- [[F133-dat]]

+

+

+## SCH

+

+

+

+

+## M2M Module

+

+

+

+| left | pin | pin | right |

+| --------- | --- | --- | ---------- |

+| MIC_P | 1 | 2 | VBAT |

+| MIC_N | 3 | 4 | GND |

+| SPK_P | 5 | 6 | NC |

+| SPK_N | 7 | 8 | USIM_VDD |

+| AGND | 9 | 10 | USIM_DATA |

+| VDD_EXT | 11 | 12 | USIM_CLK |

+| RESERVED | 13 | 14 | USIM_RST |

+| GND | 15 | 16 | RESERVED |

+| RESERVED | 17 | 18 | GND |

+| WAKEUP_IN | 19 | 20 | W_DISABLE# |

+| GND | 21 | 22 | RESET# |

+| UART_RXD | 23 | 24 | VBAT |

+| UART_RTS | 25 | 26 | GND |

+| GND | 27 | 28 | UART_CTS |

+| GND | 29 | 30 | UART_DCD |

+| UART_TXD | 31 | 32 | SLEEP_IND |

+| RESET# | 33 | 34 | GND |

+| GND | 35 | 36 | USB_DM |

+| GND | 37 | 38 | USB_DP |

+| VBAT | 39 | 40 | GND |

+| VBAT | 41 | 42 | LED_WWAN# |

+| GND | 43 | 44 | USIM_DET |

+| RESERVED | 45 | 46 | UART_DTR |

+| RESERVED | 47 | 48 | NC |

+| RESERVED | 49 | 50 | GND |

+| RESERVED | 51 | 52 | VBAT |

+

+

+

+

+| Specification | Value |

+| ------------------ | ---------------------------------------- |

+| **PCB Thickness** | **0.8 mm** (standard) |

+| **Edge Connector** | ~**0.8 mm**, beveled |

+| **Card Width** | 30 mm |

+| **Card Length** | 30 mm (Half-size) / 50.95 mm (Full-size) |

+| | fun1 | chip | left pin | right pin | chip | fun2 |

+| -------- | -------- | ---- | -------- | --------- | ---- | ------- |

+| GND | | GND | 1 | 2 | GND | GND |

+| | DVP_SDA | PE13 | 3 | 4 | GND | GND |

+| | DVP_SCL | PE12 | 5 | 6 | GND | GND |

+| UART0 rx | DVP_XCLK | PE3 | 7 | 8 | GND | GND |

+| UART0 tx | DVP_CLK | PE2 | 9 | 10 | D0+ | D0+ |

+| | DVP_Y9 | PE11 | 11 | 12 | D0- | D0- |

+| | DVP_Y8 | PE10 | 13 | 14 | PD19 | LCD_DE |

+| | DVP_Y7 | PE9 | 15 | 16 | PD18 | LCD_CLK |

+| | - | - | - | - | - | - |

+| | LCD_PWM | PD22 | 17 | 18 | PE8 | DVP_Y6 |

+| | LCD_VS | PD21 | 19 | 20 | PE7 | DVP_Y5 |

+| | LCD_HS | PD20 | 21 | 22 | PE6 | DVP_Y4 |

+| | LCD_D2 | PD0 | 23 | 24 | PE5 | DVP_Y3 |

+| | LCD_D3 | PD1 | 25 | 26 | PE4 | DVP_Y2 |

+| | LCD_D4 | PD2 | 27 | 28 | PE0 | DVP_HS |

+| | LCD_D5 | PD3 | 29 | 30 | PE1 | DVP_VS |

+| | LCD_D6 | PD4 | 31 | 32 | PD14 | LCD_D20 |

+| | LCD_D7 | PD5 | 33 | 34 | PD15 | LCD_D21 |

+| | LCD_D10 | PD6 | 35 | 36 | PD16 | LCD_D22 |

+| | LCD_D11 | PD7 | 37 | 38 | PD17 | LCD_D23 |

+| | LCD_D12 | PD8 | 39 | 40 | PB7 | |

+| | LCD_D13 | PD9 | 41 | 42 | PB6 | |

+| | LCD_D14 | PD10 | 43 | 44 | PB5 | |

+| | LCD_D15 | PD11 | 45 | 46 | PB4 | |

+| | LCD_D18 | PD12 | 47 | 48 | PB3 | CTP_INT |

+| | LCD_D19 | PD13 | 49 | 50 | PB2 | CTP_RST |

+| | VBUS | VBUS | 51 | 52 | VBUS | VBUS |

+| Pins / Signals | Function | Notes |

+| ---------------------- | ----------- | ---------------------------------- |

+| PG1 ~ PG6 ~ PG9 ~ PG15 | BT / Wi‑Fi | Bluetooth and Wi‑Fi signals |

+| PF0–PF6 | SDC0 | SD controller 0 |

+| PC2–PC7 | SPI0 | SPI bus 0 |

+| PE0–PE13 | Camera | Camera interface pins |

+| PD | LCD display | LCD interface signals |

+| audio | FPC 9P | Audio via FPC 9-pin connector |

+| touchpanel | FPC 5P | Touchpanel via FPC 5-pin connector |

+| SPI0_MOSI | Button 1 | MOSI repurposed as Button 1 |

+| RESET | Button 2 | Reset button |

+

+- [[F133-dat]]

+- [[oled-dat]] - [[amoled-dat]] - [[display-dat]]

+- [[camera-dat]] - [[DVP-display-dat]]

+## OV2640-dat

+

+| Voltage Type | set | Voltage Range |

+| ------------ | ----- | ------------- |

+| DVDD | 1.2V ? | 1.2-1.5V |

+| AVDD | 2.8V ? | 2.5-3.0V |

+| DOVDD IO | 2.8V ? | 1.7-3.3V |

+## touchpanel-SDK-dat

+

+https://github.com/alex-code/GT911

+

+

+

+

+

+

+

+

+## SY7201-dat

+

+

+

+

+

+

+

+

+

+

+

+## ref

+

+- [[LCD-dat]]

+

+- [[silergy-dat]]

+

+

+# SY7201-dat.md

+

+- [[SY7200-dat]]

+## MIPI-DSI Interface Pinout

+

+| Pin No. | Symbol | Description | When Not in Use |

+|---------|----------|------------------------------------------|----------------------|

+| 1 | LEDA | B/L positive pin | |

+| 2 | LEDK | B/L negative pin | |

+| 3 | VDD | Power supply, 2.8–3.3V type | |

+| 4 | GND | Power Ground | |

+| 5 | DON | MIPI DSI differential data pair (N) | |

+| 6 | DOP | MIPI DSI differential data pair (P) | |

+| 7 | GND | Power Ground | |

+| 8 | CLKN | MIPI DSI differential clock pair (N) | |

+| 9 | CLKP | MIPI DSI differential clock pair (P) | |

+| 10 | GND | Power Ground | |

+| 11 | D1N | MIPI DSI differential data pair 1 (N) | |

+| 12 | D1P | MIPI DSI differential data pair 1 (P) | |

+| 13–33 | GND | Power Ground | |

+| 34 | RESET | Reset the LCM | |

+| 35–37 | GND | Power Ground | |

+| 38 | VDD | Power supply, 2.8–3.3V type | |

+| 39 | GND | Power Ground | |

+| 40 | NC | Dummy | |

+

+

+

+- [[silergy-dat]] - [[SY7200-dat]] - [[SY7201-dat]]

+- [[touchpanel-dat]]

+

+- [[MIPI-dat]]

+

+

+

+

+

+

+## RGB LCD 40-Pin Interface Pinout

+

+| Pin No. | Symbol | Description | When Not in Use |

+| ------- | ------ | ---------------------------------------------- | --------------- |

+| 1 | LEDA | B/L positive pin | |

+| 2 | LEDK | B/L negative pin | |

+| 3 | VDD | Power supply, 2.8–3.3V type | |

+| 4–13 | GND | Power Ground | |

+| 14 | VS | Frame synchronizing signal | |

+| 15 | HS | Line synchronizing signal | |

+| 16 | Pclk | Dot clock signal | |

+| 17 | DE | Data enable signal for RGB interface operation | Power Ground |

+| | | Low: access enabled; High: access inhibited | |

+| 18–22 | B0–B4 | 5-bit Blue data input | |

+| 23–28 | G0–G5 | 6-bit Green data input | |

+| 29–33 | R0–R4 | 5-bit Red data input | |

+| 34 | RESET | Reset the LCM | |

+| 35 | CSA | Chip select signal | |

+| 36 | SCL | Serial clock | |

+| 37 | SDA | Serial data input/output (bidirectional pin) | |

+| 38 | GND | Power Ground | |

+| 39 | VDD | Power supply, 2.8–3.3V type | |

+| 40 | NC | Dummy | |

+

+

+## 8-bit parallel RGB LCD

+

+# Typical 8-bit Parallel TFT LCD Pinout (Example: ILI9341, ST7789V, HX8357)

+

+| Pin | Name | Function |

+| --- | ---- | ------------------------------------- |

+| 1 | A | LED anode (backlight +) |

+| 2 | K | LED cathode (backlight –) |

+| 3 | NC | No connection |

+| 4 | NC | No connection |

+| 5 | NC | No connection |

+| 6 | VCC | Power supply (usually 3.3 V or 5 V) |

+| 7 | D7 | Data bit 7 |

+| 8 | D6 | Data bit 6 |

+| 9 | D5 | Data bit 5 |

+| 10 | D4 | Data bit 4 |

+| 11 | D3 | Data bit 3 |

+| 12 | D2 | Data bit 2 |

+| 13 | D1 | Data bit 1 |

+| 14 | D0 | Data bit 0 |

+| 15 | RD | Read strobe (MCU reads data from LCD) |

+| 16 | WR | Write strobe (MCU writes data to LCD) |

+| 17 | RS | Register select / Data-Command (DC) |

+| 18 | CS | Chip select |

+| 19 | TE | Tearing effect signal (sync) |

+| 20 | RST | Reset |

+| 21 | GND | Ground |

+| 22 | GND | Ground |

+

+**Notes:**

+- **Interface type:** 8-bit parallel MCU (8080 or 6800 mode)

+- **Typical driver ICs:** ILI9341, ST7789V, HX8357

+- `A` & `K` are for LED backlight, powered separately

+- `TE` is optional and used for synchronizing to avoid tearing

+

+

+

+

+

+

+- [[LCD-dat]] - [[led-driver-dat]]

+

+

+

+

+## driver

+

+- [[ILI9341-dat]]

+

+- [[ST7789-dat]] - [[ST7735-dat]]

+

+- [[SSD1681-dat]] - [[SSD1315-dat]] - [[SSD1306-dat]] - [[SSD1312-dat]] - [[SSH1106-dat]] - [[CH1106-dat]]

+

+- [[GC9107-dat]] - [[GC9A01-dat]]

+

+- [[ILI9488-dat]] - [[ILI9486-dat]] - [[ILI9481-dat]]

+

+- [[SSD1963-dat]]

+

+- [[RA8875-dat]]

+

+- [[HX8357-dat]]

+

+

+- [[LDO-2CH-dat]]

+

+- [[OV2640-dat]]

+

+Connector

+

+24Pins Description for - [[OV3660-dat]]

+

+| Pin No. | Name | Description |

+| ------- | -------- | ---------------------- |

+| 01 | NC | - |

+| 02 | AGND | Analog Ground |

+| 03 | SIO_D | Serial Data |

+| 04 | AVDD_28 | Analog Voltage 2.8V |

+| 05 | SIO_C | Serial Clock |

+| 06 | RESET | Reset |

+| 07 | VSync | Vertical Sync |

+| 08 | PWDN | Power Down |

+| 09 | HS(HREF) | Horizontal Sync (HREF) |

+| 10 | DVDD_15 | Digital Voltage 1.5V |

+| 11 | DOVDD | Digital Output Voltage |

+| 12 | D9 | Data Bit 9 |

+| 13 | MCLK | Master Clock |

+| 14 | D8 | Data Bit 8 |

+| 15 | DGND | Digital Ground |

+| 16 | D7 | Data Bit 7 |

+| 17 | PCLK | Pixel Clock |

+| 18 | D6 | Data Bit 6 |

+| 19 | D2 | Data Bit 2 |

+| 20 | D5 | Data Bit 5 |

+| 21 | D3 | Data Bit 3 |

+| 22 | D4 | Data Bit 4 |

+| 23 | NC | - |

+| 24 | NC | - |

+

+- [[LDO-dat]]

+

+

+# DVP-display-dat

+

+no DVP display, only [[DVP-camera-dat]]

+

+## RGB Parallel Interface vs DVP Interface

+

+| Feature | RGB Parallel Interface (Display MCU Interface) | DVP Interface (Digital Video Port, Camera) |

+|----------------------|-----------------------------------------------|--------------------------------------------|

+| Data Direction | MCU → Display | Camera → MCU |

+| Data Lines | D0~D7 or D0~D15 (pixel data) | D0~D7 or D0~D9 (pixel data) |

+| Control Signals | WR / RD / RS / CS / DE / HSYNC / VSYNC | PCLK / HREF / VSYNC |

+| Timing | MCU-controlled writes (typical 8080 / 6800) | Camera outputs fixed pixel timing |

+| Use Case | TFT LCD display | CMOS camera module |

+| Interface Type | Parallel | Parallel |

+| Similarity | Both use multi-line parallel pixel transfer | Both use multi-line parallel pixel transfer|

+

+**Summary:**

+- DVP is a parallel output interface from a camera; MCU or FPGA captures image data.

+- The RGB parallel interface is a display input; MCU or FPGA drives the panel.

+- They are electrically similar, but timing and purpose differ.

+

+## Can DVP Be Used as a Display Interface?

+

+- Strictly speaking, DVP (Digital Video Port) was defined as a camera output interface for MCU/FPGA reception.

+- However, in practice some low-resolution or embedded display modules can accept DVP-style input:

+ - These modules integrate a small controller that converts incoming DVP pixel timing into the panel drive.

+ - The MCU or FPGA sends pixel data following DVP timing directly to the module.

+

+### Characteristics

+- Physical signals are similar: PCLK, VSYNC, HSYNC/HREF, data lines D0~Dn.

+- Timing still follows DVP style (one pixel per PCLK edge).

+- Common in low-resolution embedded TFT modules (e.g. 2.4", 2.8" TFT LCD).

+

+### Notes / Caveats

+- You cannot treat a high-resolution raw TFT RGB panel as a DVP display module.

+- The driving MCU/FPGA must generate DVP-like streaming timing, different from 8080/6800 register/data bus write cycles.

+- Datasheets will usually state “DVP input” or “Camera interface for MCU” if such usage is supported.

+

+**Conclusion:**

+- DVP is fundamentally a camera (image sensor) interface.

+- Some display modules are DVP-compatible, but you must adhere to DVP streaming timing and control behavior.

+

+# MIPI vs DVP Interface Comparison

+

+| Feature | MIPI (DSI / CSI) | DVP (Digital Video Port) |

+| --------------------- | ----------------------------------------------------- | ------------------------------------------------- |

+| **Type** | High-speed **serial** differential signaling | **Parallel** CMOS/TTL signaling |

+| **Data Lines** | 1–4 (sometimes 8) differential lanes + clock | Multiple parallel data lines (8, 10, 12, 16 bits) |

+| **Clock** | Embedded in protocol (Data lanes use DDR with strobe) | Separate dedicated pixel clock (PCLK) |

+| **Signal Standard** | MIPI D-PHY / C-PHY (low-voltage differential) | CMOS/TTL single-ended logic |

+| **Data Rate** | Up to several Gbps per lane | Typically < 150 MHz pixel clock |

+| **Wiring Complexity** | Fewer wires (high-speed pairs) | Many wires (one per data bit + sync) |

+| **Pins** | Very few (e.g., 4–10 total) | Many (e.g., 10–20+ total) |

+| **Sync Signals** | Embedded in packet protocol | HSYNC, VSYNC required |

+| **Protocol Layer** | Uses packet-based protocol (like networking) | Raw pixel data per clock |

+| **Power Consumption** | Lower per bit transferred (but high-speed) | Higher due to many single-ended lines |

+| **Typical Use** | Smartphones, tablets, high-res displays/cameras | Simple camera modules, low-cost LCDs |

+| **Example Devices** | MIPI-DSI display panels, MIPI-CSI2 camera sensors | OV7670 camera, parallel RGB LCD panels |

+

+

+

+

+

+

+

+**DVP** in the display context usually refers to the **Digital Video Port** interface. - [[parallel-display-dat]]

+It’s a **parallel interface** commonly used in cameras, simple LCDs, or microcontroller-driven displays.

+

+## How it works

+

+

+- Transfers **pixel data** in parallel (8, 16, or 24 data lines, depending on color depth).

+- Uses **synchronization signals**:

+ - **HSYNC** (Horizontal Sync) – signals the start of a new line

+ - **VSYNC** (Vertical Sync) – signals the start of a new frame

+ - **PCLK** (Pixel Clock) – latches each pixel’s data

+- Can work with formats like **RGB565**, **RGB888**, or **YUV422**.

+

+## Key Characteristics

+1. **Simple protocol** – no complex packetization (unlike MIPI-DSI).

+2. **Lower speed** – parallel clock typically in the tens of MHz.

+3. **More pins needed** – due to multiple parallel data lines.

+4. **Used in MCUs and simple SoCs** – no need for high-speed serializers.

+

+## Common Uses

+

+

+- Cheap TFT LCD modules with MCU controllers

+- CMOS camera modules with parallel output

+- Low-resolution displays in industrial or hobby projects

+

+## Comparison (DVP vs MIPI-DSI)

+

+| Feature | DVP (Digital Video Port) | MIPI-DSI |

+| ------------- | -------------------------- | ----------------------------------- |

+| Data Transfer | Parallel (8–24 data lines) | High-speed serial (2–4 lanes) |

+| Speed | Tens of MHz | Hundreds of MHz to Gbps |

+| Pin Count | High | Low |

+| Complexity | Simple | Complex, packetized |

+| Use Case | Simple displays, cameras | High-res smartphone/tablet displays |

+

+## SCH

+

+- [[F133-dat]]

+

+8-bit Y2 ~ Y9 // HSYNC + VSYNC + PCLK + XCLK + SCL + SDA + **RST

+

+

+

+

+

+## DVP Display 22-Pin Interface

+

+6 bit version

+

+| Pin No. | Symbol | Description |

+| ------- | ------ | ------------------------ |

+| 1 | VCC | Power supply |

+| 2 | GND | Ground |

+| 3 | RST | Reset |

+| 4 | CS | Chip select |

+| 5 | SCL | Serial clock |

+| 6 | VS | Vertical sync |

+| 7 | HS | Horizontal sync |

+| 8 | DE | Data enable |

+| 9 | DLCK | Data clock (pixel clock) |

+| 10 | SDA | Serial data |

+| 11 | K | Backlight control (LEDK) |

+| 12 | A | Backlight control (LEDA) |

+| 13 | D0 | Data bit 0 |

+| 14 | D1 | Data bit 1 |

+| 15 | D2 | Data bit 2 |

+| 16 | D3 | Data bit 3 |

+| 17 | D4 | Data bit 4 |

+| 18 | D5 | Data bit 5 |

+| 19 | NC | - |

+| 20 | NC | - |

+| 21 | NC | - |

+| 22 | NC | - |

+

+

+## ref

+

+- [[parallel-display-dat]]

+- [[XC6206-dat]]

+

+## ref

+

+- [[LDO-2CH]]