Board-dat/CCO/CCO3626-dat/CCO3626-dat.md
... ...
@@ -1,6 +1,13 @@
1 1
2 2
# CCO3626
3 3
4
+
5
+- [[CCO3626-dat]] - [[CCO3627-dat]] - [[CCO3628-dat]] - [[CCO3629-dat]] - [[DPR1016-dat]]
6
+
7
+https://www.electrodragon.com/product-category/modules/programmer/ic-socket-programmer/
8
+
9
+
10
+
4 11
- SOP8 150 mil = 3.9 mm
5 12
- supported chips：24CXX、93CXX
6 13
Board-dat/CCO/CCO3627-dat/CCO3627-dat.md
... ...
@@ -1,6 +1,11 @@
1 1
2 2
# CCO3627-dat
3 3
4
+- [[CCO3626-dat]] - [[CCO3627-dat]] - [[CCO3628-dat]] - [[CCO3629-dat]] - [[DPR1016-dat]]
5
+
6
+https://www.electrodragon.com/product-category/modules/programmer/ic-socket-programmer/
7
+
8
+
4 9
5 10
- [[footprint-dat]]
6 11
... ...
@@ -30,4 +35,5 @@
30 35
## ref
31 36
32 37
- [[CCO3626-dat]] - [[CCO3627-dat]]
38
+
33 39
- [[CCO3627]]
... ...
\ No newline at end of file
Board-dat/CCO/CCO3628-dat/CCO3628-dat.md
... ...
@@ -1,6 +1,13 @@
1 1
2 2
# CCO3628-dat
3 3
4
+
5
+- [[CCO3626-dat]] - [[CCO3627-dat]] - [[CCO3628-dat]] - [[CCO3629-dat]] - [[DPR1016-dat]]
6
+
7
+https://www.electrodragon.com/product-category/modules/programmer/ic-socket-programmer/
8
+
9
+
10
+
4 11
- [[footprint-dat]]
5 12
6 13
Board-dat/CCO/CCO3629-dat/CCO3629-dat.md
... ...
@@ -1,6 +1,13 @@
1 1
2 2
# CCO3629-dat
3 3
4
+
5
+- [[CCO3626-dat]] - [[CCO3627-dat]] - [[CCO3628-dat]] - [[CCO3629-dat]] - [[DPR1016-dat]]
6
+
7
+https://www.electrodragon.com/product-category/modules/programmer/ic-socket-programmer/
8
+
9
+
10
+
4 11
- [[footprint-dat]]
5 12
6 13
Board-dat/DPR/DPR1016-dat/DPR1016-dat.md
... ...
@@ -9,6 +9,14 @@
9 9
10 10
### Board Map, Dimension, Pins, chip info, Use Guide, Setup Jumper, etc.
11 11
12
+- [[CCO3626-dat]] - [[CCO3627-dat]] - [[CCO3628-dat]] - [[CCO3629-dat]] - [[DPR1016-dat]]
13
+
14
+https://www.electrodragon.com/product-category/modules/programmer/ic-socket-programmer/
15
+
16
+
17
+
18
+
19
+
12 20
- [[TQFP32-dat]] - [[TQFP-dat]] - [[footprint-dat]]
13 21
14 22
covert map
Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/2026-02-11-02-42-37.png
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Binary files /dev/null and b/Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/2026-02-11-02-42-37.png differ
Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/2026-02-11-02-45-22.png
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Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/2026-02-11-02-58-41.png
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Binary files /dev/null and b/Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/2026-02-11-02-58-41.png differ
Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/LGT8F328-SDK-DAT.md
... ...
@@ -7,6 +7,65 @@
7 7
8 8
- [[VisualGDB]]
9 9
10
+- [[programmer-socket-dat]]
11
+
12
+- [[CH55x-dat]]
13
+
14
+## SWDICE
15
+
16
+![](2026-02-11-02-42-37.png)
17
+
18
+Connect your new programming device to the board to be programmed (“target”) as follows:
19
+
20
+| Programmer | Target |
21
+| ------------ | ------ |
22
+| GND | GND |
23
+| 5V | VCC |
24
+| Pin 12 (D12) | SWD |
25
+| Pin 10 (D10) | RST |
26
+| Pin 13 (D13) | SWC |
27
+
28
+
29
+- [[SWDICE-dat]]
30
+
31
+![](2026-02-11-02-45-22.png)
32
+
33
+![](2026-02-11-02-58-41.png)
34
+
35
+### SISP
36
+
37
+- connect pin 18 AVCC and pin 21 GND
38
+ SISP 模式为在线烧写模式， 可以支持 LGT 目前除 LGT8F08A 以为的所有芯片，也将
39
+支持 LGT 未来发布的芯片。这种模式下，SWDICE_mkII Pro 为 WinUSB 设备，只能够通过
40
+LGTMix_ISP 工具访问，但需要使用 3.x 以上的版本。
41
+
42
+
43
+ SISP 模式下，SWDICE_mkII Pro 在 Windows 8/10 系统下无需驱动，操作系统自带 winusb
44
+设备驱动。在 Windows XP/7 系统下， 需要安装 SWDISP_mkII 驱动程序。SWDISP_mkII 驱动
45
+可通过官网下载， 或者与我们联系获得。
46
+
47
+ 另外两种模式为调试器模式。分别用于调试 LGT8X/AVR 内核以及 MIC8X/PIC 内核系列芯
48
+片。调试器模式下，SWDICE_mkII Pro 工作于专用 USB 设备，需要由相应的开发环境以及调
49
+试器驱动支持。一般安装开发环境会同时安装调试器所需驱动，无需单独安装。
50
+
51
+### SICE
52
+
53
+ SICE 模式用于调试 LGT8X/AVR 内核芯片。包括 LGT8F08A，LGT8F88A/B，LGT8FX8D 系
54
+列芯片，以及未来所有 LGT 基于 LGT8X/AVR 内核的所有芯片。
55
+ SICE 模式下， SWDICE_mkII Pro 将会被枚举为 JTAGICE_mkII 设备，可以配合 AVRStudio
56
+4/5/6/7 或者 IAR workbench for AVR 实现芯片的在线调试。安装开发环境后，将同时安装调
57
+试器相关驱动。如果需要单独安装，可以在我们的官网下载 driver-atmel--bundle-7.0.888 驱
58
+动安装程序。
59
+
60
+### ICSP
61
+
62
+ ICSP 模式用于调试 MIC8X/PIC 内核芯片。目前 LGT 基于 MIC8X/PIC 内核的芯片包括
63
+LGT8P653A/663A，LGT8F684A。但这些芯片都不支持在线调试。因此此功能暂时不可用。在
64
+LGT 后续发布支持在线调试的 MIC8X 内核芯片，我们将提供固件升级以支持 ICSP 在线调试
65
+功能。因此对于目前的 LGT8P653/663A 以及 LGT8F684A 芯片，请使用 SISP 在线烧写模式。
66
+
67
+
68
+
10 69
## programming interface
11 70
12 71
- GND2/AREF/`SWD`/PE2
Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/optiboot_lgt8fx8p/Makefile
... ...
@@ -0,0 +1,650 @@
1
+# Makefile for ATmegaBOOT
2
+# E.Lins, 18.7.2005
3
+# $Id$
4
+#
5
+# Instructions
6
+#
7
+# To make bootloader .hex file:
8
+# make diecimila
9
+# make lilypad
10
+# make ng
11
+# etc...
12
+#
13
+# To burn bootloader .hex file:
14
+# make diecimila_isp
15
+# make lilypad_isp
16
+# make ng_isp
17
+# etc...
18
+#
19
+# Edit History
20
+# 201303xx: WestfW: Major Makefile restructuring.
21
+# Allows options on Make command line "make xx LED=B3"
22
+# (see also pin_defs.h)
23
+# Divide into "chip" targets and "board" targets.
24
+# Most boards are (recursive) board targets with options.
25
+# Move isp target to separate makefile (fixes m8 EFUSE)
26
+# Some (many) targets will now be rebuilt when not
27
+# strictly necessary, so that options will be included.
28
+# (any "make" with options will always compile.)
29
+# Set many variables with ?= so they can be overridden
30
+# Use arduinoISP settings as default for ISP targets
31
+#
32
+
33
+#----------------------------------------------------------------------
34
+#
35
+# program name should not be changed...
36
+PROGRAM = optiboot
37
+
38
+# The default behavior is to build using tools that are in the users
39
+# current path variables, but we can also build using an installed
40
+# Arduino user IDE setup, or the Arduino source tree.
41
+# Uncomment this next lines to build within the arduino environment,
42
+# using the arduino-included avrgcc toolset (mac and pc)
43
+# ENV ?= arduinodev
44
+# OS ?= windows
45
+
46
+# export symbols to recursive makes (for ISP)
47
+export
48
+
49
+# defaults
50
+EXT_OSC = 0
51
+MCU_TARGET = atmega168
52
+LDSECTIONS = -Wl,--section-start=.text=0x3e00 -Wl,--section-start=.version=0x3ffe
53
+
54
+# Build environments
55
+# Start of some ugly makefile-isms to allow optiboot to be built
56
+# in several different environments. See the README.TXT file for
57
+# details.
58
+
59
+# default
60
+fixpath = $(1)
61
+
62
+ifeq ($(ENV), arduino)
63
+# For Arduino, we assume that we're connected to the optiboot directory
64
+# included with the arduino distribution, which means that the full set
65
+# of avr-tools are "right up there" in standard places.
66
+TOOLROOT = /Applications/Arduino.app/Contents/Resources/Java/hardware/tools/avr
67
+GCCROOT = $(TOOLROOT)/avr/bin/
68
+
69
+ifeq ($(OS), windows)
70
+# On windows, SOME of the tool paths will need to have backslashes instead
71
+# of forward slashes (because they use windows cmd.exe for execution instead
72
+# of a unix/mingw shell?) We also have to ensure that a consistent shell
73
+# is used even if a unix shell is installed (ie as part of WINAVR)
74
+fixpath = $(subst /,\,$1)
75
+SHELL = cmd.exe
76
+endif
77
+
78
+else ifeq ($(ENV), arduinodev)
79
+# Arduino IDE source code environment. Use the unpacked compilers created
80
+# by the build (you'll need to do "ant build" first.)
81
+ifeq ($(OS), macosx)
82
+TOOLROOT = ../../../../build/macosx/work/Arduino.app/Contents/Resources/Java/hardware/tools
83
+endif
84
+ifeq ($(OS), windows)
85
+TOOLROOT = ../../../../build/windows/work/hardware/tools
86
+endif
87
+
88
+GCCROOT = $(TOOLROOT)/avr/bin/
89
+AVRDUDE_CONF = -C$(TOOLROOT)/avr/etc/avrdude.conf
90
+
91
+else
92
+TOOLROOT =
93
+GCCROOT =
94
+AVRDUDE_CONF =
95
+endif
96
+
97
+STK500 = "C:\Program Files\Atmel\AVR Tools\STK500\Stk500.exe"
98
+STK500-1 = $(STK500) -e -d$(MCU_TARGET) -pf -vf -if$(PROGRAM)_$(TARGET).hex \
99
+ -lFF -LFF -f$(HFUSE)$(LFUSE) -EF8 -ms -q -cUSB -I200kHz -s -wt
100
+STK500-2 = $(STK500) -d$(MCU_TARGET) -ms -q -lCF -LCF -cUSB -I200kHz -s -wt
101
+#
102
+# End of build environment code.
103
+
104
+
105
+OBJ = $(PROGRAM).o
106
+OPTIMIZE = -Os -fno-inline-small-functions -fno-split-wide-types -mshort-calls
107
+
108
+DEFS =
109
+LIBS =
110
+
111
+CC = $(GCCROOT)avr-gcc
112
+
113
+# Override is only needed by avr-lib build system.
114
+
115
+override CFLAGS = -g -Wall $(OPTIMIZE) -mmcu=$(MCU_TARGET) -DF_CPU=$(AVR_FREQ) $(DEFS)
116
+override LDFLAGS = $(LDSECTIONS) -Wl,--relax -nostartfiles -nostdlib
117
+#-Wl,--gc-sections
118
+
119
+OBJCOPY = $(GCCROOT)avr-objcopy
120
+OBJDUMP = $(call fixpath,$(GCCROOT)avr-objdump)
121
+
122
+SIZE = $(GCCROOT)avr-size
123
+
124
+#
125
+# Make command-line Options.
126
+# Permit commands like "make atmega328 LED_START_FLASHES=10" to pass the
127
+# appropriate parameters ("-DLED_START_FLASHES=10") to gcc
128
+#
129
+
130
+ifdef BAUD_RATE
131
+BAUD_RATE_CMD = -DBAUD_RATE=$(BAUD_RATE)
132
+dummy = FORCE
133
+else
134
+#BAUD_RATE_CMD = -DBAUD_RATE=115200
135
+BAUD_RATE_CMD = -DBAUD_RATE=57600
136
+#BAUD_RATE_CMD = -DBAUD_RATE=38400
137
+#BAUD_RATE_CMD = -DBAUD_RATE=19200
138
+endif
139
+
140
+#
141
+# External crystal
142
+#
143
+
144
+ifdef EXT_OSC
145
+OSC_CMD = -DEXT_OSC=$(EXT_OSC)
146
+else
147
+OSC_CMD = -DEXT_OSC=0
148
+endif
149
+
150
+ifdef LED_START_FLASHES
151
+LED_START_FLASHES_CMD = -DLED_START_FLASHES=$(LED_START_FLASHES)
152
+dummy = FORCE
153
+else
154
+LED_START_FLASHES_CMD = -DLED_START_FLASHES=3
155
+endif
156
+
157
+# BIG_BOOT: Include extra features, up to 1K.
158
+ifdef BIGBOOT
159
+BIGBOOT_CMD = -DBIGBOOT=1
160
+dummy = FORCE
161
+endif
162
+
163
+ifdef SOFT_UART
164
+SOFT_UART_CMD = -DSOFT_UART=1
165
+dummy = FORCE
166
+endif
167
+
168
+ifdef LED_DATA_FLASH
169
+LED_DATA_FLASH_CMD = -DLED_DATA_FLASH=1
170
+dummy = FORCE
171
+#else
172
+#LED_DATA_FLASH_CMD= -DLED_DATA_FLASH=1
173
+endif
174
+
175
+ifdef LED
176
+LED_CMD = -DLED=$(LED)
177
+dummy = FORCE
178
+endif
179
+
180
+ifdef SINGLESPEED
181
+SSCMD = -DSINGLESPEED=1
182
+endif
183
+
184
+COMMON_OPTIONS = $(BAUD_RATE_CMD) $(LED_START_FLASHES_CMD) $(BIGBOOT_CMD)
185
+COMMON_OPTIONS += $(SOFT_UART_CMD) $(LED_DATA_FLASH_CMD) $(LED_CMD) $(SSCMD)
186
+COMMON_OPTIONS += $(OSC_CMD)
187
+
188
+#UART is handled separately and only passed for devices with more than one.
189
+ifdef UART
190
+UARTCMD = -DUART=$(UART)
191
+endif
192
+
193
+# Not supported yet
194
+# ifdef SUPPORT_EEPROM
195
+# SUPPORT_EEPROM_CMD = -DSUPPORT_EEPROM
196
+# dummy = FORCE
197
+# endif
198
+
199
+# Not supported yet
200
+# ifdef TIMEOUT_MS
201
+# TIMEOUT_MS_CMD = -DTIMEOUT_MS=$(TIMEOUT_MS)
202
+# dummy = FORCE
203
+# endif
204
+#
205
+
206
+#---------------------------------------------------------------------------
207
+# "Chip-level Platform" targets.
208
+# A "Chip-level Platform" compiles for a particular chip, but probably does
209
+# not have "standard" values for things like clock speed, LED pin, etc.
210
+# Makes for chip-level platforms should usually explicitly define their
211
+# options like: "make atmega1285 AVR_FREQ=16000000L LED=D0"
212
+#---------------------------------------------------------------------------
213
+#
214
+# Note about fuses:
215
+# the efuse should really be 0xf8; since, however, only the lower
216
+# three bits of that byte are used on the atmega168, avrdude gets
217
+# confused if you specify 1's for the higher bits, see:
218
+# http://tinker.it/now/2007/02/24/the-tale-of-avrdude-atmega168-and-extended-bits-fuses/
219
+#
220
+# similarly, the lock bits should be 0xff instead of 0x3f (to
221
+# unlock the bootloader section) and 0xcf instead of 0x2f (to
222
+# lock it), but since the high two bits of the lock byte are
223
+# unused, avrdude would get confused.
224
+#---------------------------------------------------------------------------
225
+#
226
+
227
+# Test platforms
228
+# Virtual boot block test
229
+virboot328: TARGET = atmega328
230
+virboot328: MCU_TARGET = atmega328p
231
+virboot328: CFLAGS += $(COMMON_OPTIONS) '-DVIRTUAL_BOOT'
232
+virboot328: AVR_FREQ ?= 16000000L
233
+virboot328: LDSECTIONS = -Wl,--section-start=.text=0x7e00 -Wl,--section-start=.version=0x7ffe
234
+virboot328: $(PROGRAM)_atmega328.hex
235
+virboot328: $(PROGRAM)_atmega328.lst
236
+
237
+# Diecimila, Duemilanove with m168, and NG use identical bootloaders
238
+# Call it "atmega168" for generality and clarity, keep "diecimila" for
239
+# backward compatibility of makefile
240
+#
241
+atmega168: TARGET = atmega168
242
+atmega168: MCU_TARGET = atmega168
243
+atmega168: CFLAGS += $(COMMON_OPTIONS)
244
+atmega168: AVR_FREQ ?= 16000000L
245
+atmega168: $(PROGRAM)_atmega168.hex
246
+atmega168: $(PROGRAM)_atmega168.lst
247
+
248
+atmega168_isp: atmega168
249
+atmega168_isp: TARGET = atmega168
250
+# 2.7V brownout
251
+atmega168_isp: HFUSE ?= DD
252
+# Low power xtal (16MHz) 16KCK/14CK+65ms
253
+atmega168_isp: LFUSE ?= FF
254
+# 512 byte boot
255
+atmega168_isp: EFUSE ?= 04
256
+atmega168_isp: isp
257
+
258
+atmega328: TARGET = atmega328
259
+atmega328: MCU_TARGET = atmega328p
260
+atmega328: CFLAGS += $(COMMON_OPTIONS)
261
+atmega328: AVR_FREQ ?= 16000000L
262
+atmega328: LDSECTIONS = -Wl,--section-start=.text=0x7e00 -Wl,--section-start=.version=0x7ffe
263
+atmega328: $(PROGRAM)_atmega328.hex
264
+atmega328: $(PROGRAM)_atmega328.lst
265
+
266
+atmega328_isp: atmega328
267
+atmega328_isp: TARGET = atmega328
268
+atmega328_isp: MCU_TARGET = atmega328p
269
+# 512 byte boot, SPIEN
270
+atmega328_isp: HFUSE ?= DE
271
+# Low power xtal (16MHz) 16KCK/14CK+65ms
272
+atmega328_isp: LFUSE ?= FF
273
+# 2.7V brownout
274
+atmega328_isp: EFUSE ?= FD
275
+atmega328_isp: isp
276
+
277
+atmega644p: TARGET = atmega644p
278
+atmega644p: MCU_TARGET = atmega644p
279
+atmega644p: CFLAGS += $(COMMON_OPTIONS) -DBIGBOOT $(LED_CMD)
280
+atmega644p: AVR_FREQ ?= 16000000L
281
+atmega644p: LDSECTIONS = -Wl,--section-start=.text=0xfc00 -Wl,--section-start=.version=0xfffe
282
+atmega644p: CFLAGS += $(UARTCMD)
283
+atmega644p: $(PROGRAM)_atmega644p.hex
284
+atmega644p: $(PROGRAM)_atmega644p.lst
285
+
286
+atmega1284: TARGET = atmega1284p
287
+atmega1284: MCU_TARGET = atmega1284p
288
+atmega1284: CFLAGS += $(COMMON_OPTIONS) -DBIGBOOT $(LED_CMD)
289
+atmega1284: AVR_FREQ ?= 16000000L
290
+atmega1284: LDSECTIONS = -Wl,--section-start=.text=0x1fc00 -Wl,--section-start=.version=0x1fffe
291
+atmega1284: CFLAGS += $(UARTCMD)
292
+atmega1284: $(PROGRAM)_atmega1284p.hex
293
+atmega1284: $(PROGRAM)_atmega1284p.lst
294
+
295
+atmega1284p: atmega1284
296
+
297
+atmega1284_isp: atmega1284
298
+atmega1284_isp: TARGET = atmega1284p
299
+atmega1284_isp: MCU_TARGET = atmega1284p
300
+# 1024 byte boot
301
+atmega1284_isp: HFUSE ?= DE
302
+# Full Swing xtal (16MHz) 16KCK/14CK+65ms
303
+atmega1284_isp: LFUSE ?= F7
304
+# 2.7V brownout
305
+atmega1284_isp: EFUSE ?= FD
306
+atmega1284_isp: isp
307
+
308
+#Atmega1280
309
+atmega1280: MCU_TARGET = atmega1280
310
+atmega1280: CFLAGS += $(COMMON_OPTIONS) -DBIGBOOT $(UART_CMD)
311
+atmega1280: AVR_FREQ ?= 16000000L
312
+atmega1280: LDSECTIONS = -Wl,--section-start=.text=0x1fc00 -Wl,--section-start=.version=0x1fffe
313
+atmega1280: $(PROGRAM)_atmega1280.hex
314
+atmega1280: $(PROGRAM)_atmega1280.lst
315
+
316
+
317
+# ATmega8
318
+#
319
+atmega8: TARGET = atmega8
320
+atmega8: MCU_TARGET = atmega8
321
+atmega8: CFLAGS += $(COMMON_OPTIONS)
322
+atmega8: AVR_FREQ ?= 16000000L
323
+atmega8: LDSECTIONS = -Wl,--section-start=.text=0x1e00 -Wl,--section-start=.version=0x1ffe
324
+atmega8: $(PROGRAM)_atmega8.hex
325
+atmega8: $(PROGRAM)_atmega8.lst
326
+
327
+atmega8_isp: atmega8
328
+atmega8_isp: TARGET = atmega8
329
+atmega8_isp: MCU_TARGET = atmega8
330
+# SPIEN, CKOPT (for full swing xtal), Bootsize=512B
331
+atmega8_isp: HFUSE ?= CC
332
+# 2.7V brownout, 16MHz Xtal, 16KCK/14CK+65ms
333
+atmega8_isp: LFUSE ?= BF
334
+atmega8_isp: isp
335
+
336
+# LGT8F328P
337
+#
338
+lgt8f328p: EXT_OSC ?= 0
339
+lgt8f328p: TARGET = lgt8f328p
340
+lgt8f328p: MCU_TARGET = atmega328p
341
+lgt8f328p: CFLAGS += $(COMMON_OPTIONS)
342
+#lgt8f328p: CFLAGS += $(COMMON_OPTIONS) '-DSOFT_UART'
343
+lgt8f328p: CFLAGS += '-DVIRTUAL_BOOT_PARTITION'
344
+lgt8f328p: AVR_FREQ ?= 16000000L
345
+lgt8f328p: LDSECTIONS = -Wl,--section-start=.bootv=0x0
346
+lgt8f328p: LDSECTIONS += -Wl,--section-start=.text=0x7400 -Wl,--section-start=.version=0x77fe
347
+lgt8f328p: $(PROGRAM)_lgt8f328p.elf
348
+lgt8f328p: $(PROGRAM)_lgt8f328p.hex
349
+lgt8f328p: $(PROGRAM)_lgt8f328p.lst
350
+
351
+lgt8f328p_isp: lgt8f328p
352
+lgt8f328p_isp: TARGET = lgt8f328p
353
+lgt8f328p_isp: MCU_TARGET = atmega323p
354
+lgt8f328p_isp: isp
355
+
356
+atmega32: TARGET = atmega32
357
+atmega32: MCU_TARGET = atmega32
358
+atmega32: CFLAGS += $(COMMON_OPTIONS)
359
+atmega32: AVR_FREQ ?= 11059200L
360
+atmega32: LDSECTIONS = -Wl,--section-start=.text=0x7e00 -Wl,--section-start=.version=0x7ffe
361
+atmega32: $(PROGRAM)_atmega32.hex
362
+atmega32: $(PROGRAM)_atmega32.lst
363
+
364
+atmega32_isp: atmega32
365
+atmega32_isp: TARGET = atmega32
366
+atmega32_isp: MCU_TARGET = atmega32
367
+# No OCD or JTAG, SPIEN, CKOPT (for full swing xtal), Bootsize=512B
368
+atmega32_isp: HFUSE ?= CE
369
+# 2.7V brownout, 16MHz Xtal, 16KCK/14CK+65ms
370
+atemga32_isp: LFUSE ?= BF
371
+atmega32_isp: isp
372
+
373
+#---------------------------------------------------------------------------
374
+# "Board-level Platform" targets.
375
+# A "Board-level Platform" implies a manufactured platform with a particular
376
+# AVR_FREQ, LED, and so on. Parameters are not particularly changable from
377
+# the "make" command line.
378
+# Most of the board-level platform builds should envoke make recursively
379
+# appropriate specific options
380
+#---------------------------------------------------------------------------
381
+# 20MHz clocked platforms
382
+#
383
+# These are capable of 230400 baud, or 115200 baud on PC (Arduino Avrdude issue)
384
+#
385
+
386
+pro20: TARGET = pro_20mhz
387
+pro20: CHIP = atmega168
388
+pro20:
389
+ $(MAKE) atmega168 AVR_FREQ=20000000L LED_START_FLASHES=3
390
+ mv $(PROGRAM)_$(CHIP).hex $(PROGRAM)_$(TARGET).hex
391
+ mv $(PROGRAM)_$(CHIP).lst $(PROGRAM)_$(TARGET).lst
392
+
393
+pro20_isp: pro20
394
+pro20_isp: TARGET = pro_20mhz
395
+# 2.7V brownout
396
+pro20_isp: HFUSE ?= DD
397
+# Full swing xtal (20MHz) 258CK/14CK+4.1ms
398
+pro20_isp: LFUSE ?= C6
399
+# 512 byte boot
400
+pro20_isp: EFUSE ?= 04
401
+pro20_isp: isp
402
+
403
+# 16MHz clocked platforms
404
+#
405
+# These are capable of 230400 baud, or 115200 baud on PC (Arduino Avrdude issue)
406
+#
407
+
408
+pro16: TARGET = pro_16MHz
409
+pro16: CHIP = atmega168
410
+pro16:
411
+ $(MAKE) $(CHIP) AVR_FREQ=16000000L LED_START_FLASHES=3
412
+ mv $(PROGRAM)_$(CHIP).hex $(PROGRAM)_$(TARGET).hex
413
+ mv $(PROGRAM)_$(CHIP).lst $(PROGRAM)_$(TARGET).lst
414
+
415
+pro16_isp: pro16
416
+pro16_isp: TARGET = pro_16MHz
417
+# 2.7V brownout
418
+pro16_isp: HFUSE ?= DD
419
+# Full swing xtal (20MHz) 258CK/14CK+4.1ms
420
+pro16_isp: LFUSE ?= C6
421
+# 512 byte boot
422
+pro16_isp: EFUSE ?= 04
423
+pro16_isp: isp
424
+
425
+diecimila: TARGET = diecimila
426
+diecimila: CHIP = atmega168
427
+diecimila:
428
+ $(MAKE) $(CHIP) AVR_FREQ=16000000L LED_START_FLASHES=3
429
+ mv $(PROGRAM)_$(CHIP).hex $(PROGRAM)_$(TARGET).hex
430
+ mv $(PROGRAM)_$(CHIP).lst $(PROGRAM)_$(TARGET).lst
431
+
432
+diecimila_isp: diecimila
433
+diecimila_isp: TARGET = diecimila
434
+# 2.7V brownout
435
+diecimila_isp: HFUSE ?= DD
436
+# Low power xtal (16MHz) 16KCK/14CK+65ms
437
+diecimila_isp: LFUSE ?= FF
438
+# 512 byte boot
439
+diecimila_isp: EFUSE ?= 04
440
+diecimila_isp: isp
441
+
442
+# Sanguino has a minimum boot size of 1024 bytes, so enable extra functions
443
+#
444
+sanguino: TARGET = $@
445
+sanguino: CHIP = atmega644p
446
+sanguino:
447
+ $(MAKE) $(CHIP) AVR_FREQ=16000000L LED=B0
448
+ mv $(PROGRAM)_$(CHIP).hex $(PROGRAM)_$(TARGET).hex
449
+ mv $(PROGRAM)_$(CHIP).lst $(PROGRAM)_$(TARGET).lst
450
+
451
+sanguino_isp: sanguino
452
+sanguino_isp: TARGET = sanguino
453
+sanguino_isp: MCU_TARGET = atmega644p
454
+# 1024 byte boot
455
+sanguino_isp: HFUSE ?= DE
456
+# Full swing xtal (16MHz) 16KCK/14CK+65ms
457
+sanguino_isp: LFUSE ?= F7
458
+# 2.7V brownout
459
+sanguino_isp: EFUSE ?= FD
460
+sanguino_isp: isp
461
+
462
+mighty1284: TARGET = $@
463
+mighty1284: CHIP = atmega1284p
464
+mighty1284:
465
+ $(MAKE) $(CHIP) AVR_FREQ=16000000L LED=B7
466
+ mv $(PROGRAM)_$(CHIP).hex $(PROGRAM)_$(TARGET).hex
467
+ mv $(PROGRAM)_$(CHIP).lst $(PROGRAM)_$(TARGET).lst
468
+
469
+mighty1284_isp: mighty1284
470
+mighty1284_isp: TARGET = mighty1284
471
+mighty1284_isp: MCU_TARGET = atmega1284p
472
+# 1024 byte boot
473
+mighty1284_isp: HFUSE ?= DE
474
+# Full swing xtal (16MHz) 16KCK/14CK+65ms
475
+mighty1284_isp: LFUSE ?= F7
476
+# 2.7V brownout
477
+mighty1284_isp: EFUSE ?= FD
478
+mighty1284_isp: isp
479
+
480
+bobuino: TARGET = $@
481
+bobuino: CHIP = atmega1284p
482
+bobuino:
483
+ $(MAKE) $(CHIP) AVR_FREQ=16000000L LED=B5
484
+ mv $(PROGRAM)_$(CHIP).hex $(PROGRAM)_$(TARGET).hex
485
+ mv $(PROGRAM)_$(CHIP).lst $(PROGRAM)_$(TARGET).lst
486
+
487
+bobuino_isp: bobuino
488
+bobuino_isp: TARGET = bobuino
489
+bobuino_isp: MCU_TARGET = atmega1284p
490
+# 1024 byte boot
491
+bobuino_isp: HFUSE ?= DE
492
+# Full swing xtal (16MHz) 16KCK/14CK+65ms
493
+bobuino_isp: LFUSE ?= F7
494
+# 2.7V brownout
495
+bobuino_isp: EFUSE ?= FD
496
+bobuino_isp: isp
497
+
498
+# MEGA1280 Board (this is different from the atmega1280 chip platform)
499
+# Mega has a minimum boot size of 1024 bytes, so enable extra functions
500
+# Note that optiboot does not (can not) work on the MEGA2560
501
+#mega: TARGET = atmega1280
502
+mega1280: atmega1280
503
+
504
+
505
+mega1280_isp: mega1280
506
+mega1280_isp: TARGET = atmega1280
507
+mega1280_isp: MCU_TARGET = atmega1280
508
+# 1024 byte boot
509
+mega1280_isp: HFUSE ?= DE
510
+# Low power xtal (16MHz) 16KCK/14CK+65ms
511
+mega1280_isp: LFUSE ?= FF
512
+# 2.7V brownout; wants F5 for some reason...
513
+mega1280_isp: EFUSE ?= F5
514
+mega1280_isp: isp
515
+
516
+# 8MHz clocked platforms
517
+#
518
+# These are capable of 115200 baud
519
+# Note that "new" Arduinos with an AVR as USB/Serial converter will NOT work
520
+# with an 8MHz target Arduino. The bitrate errors are in opposite directions,
521
+# and total too large a number.
522
+#
523
+
524
+lilypad: TARGET = $@
525
+lilypad: CHIP = atmega168
526
+lilypad:
527
+ $(MAKE) $(CHIP) AVR_FREQ=8000000L LED_START_FLASHES=3
528
+ mv $(PROGRAM)_$(CHIP).hex $(PROGRAM)_$(TARGET).hex
529
+ mv $(PROGRAM)_$(CHIP).lst $(PROGRAM)_$(TARGET).lst
530
+
531
+lilypad_isp: lilypad
532
+lilypad_isp: TARGET = lilypad
533
+# 2.7V brownout
534
+lilypad_isp: HFUSE ?= DD
535
+# Internal 8MHz osc (8MHz) Slow rising power
536
+lilypad_isp: LFUSE ?= E2
537
+# 512 byte boot
538
+lilypad_isp: EFUSE ?= 04
539
+lilypad_isp: isp
540
+
541
+# lilypad_resonator is the same as a 8MHz lilypad, except for fuses.
542
+lilypad_resonator: lilypad
543
+
544
+lilypad_resonator_isp: lilypad
545
+lilypad_resonator_isp: TARGET = lilypad
546
+# 2.7V brownout
547
+lilypad_resonator_isp: HFUSE ?= DD
548
+# Full swing xtal (20MHz) 258CK/14CK+4.1ms
549
+lilypad_resonator_isp: LFUSE ?= C6
550
+# 512 byte boot
551
+lilypad_resonator_isp: EFUSE ?= 04
552
+lilypad_resonator_isp: isp
553
+
554
+pro8: TARGET = pro_8MHz
555
+pro8: CHIP = atmega168
556
+pro8:
557
+ $(MAKE) $(CHIP) AVR_FREQ=8000000L LED_START_FLASHES=3
558
+ mv $(PROGRAM)_$(CHIP).hex $(PROGRAM)_$(TARGET).hex
559
+ mv $(PROGRAM)_$(CHIP).lst $(PROGRAM)_$(TARGET).lst
560
+
561
+pro8_isp: pro8
562
+pro8_isp: TARGET = pro_8MHz
563
+# 2.7V brownout
564
+pro8_isp: HFUSE ?= DD
565
+# Full swing xtal (20MHz) 258CK/14CK+4.1ms
566
+pro8_isp: LFUSE ?= C6
567
+# 512 byte boot
568
+pro8_isp: EFUSE ?= 04
569
+pro8_isp: isp
570
+
571
+atmega328_pro8: TARGET = atmega328_pro_8MHz
572
+atmega328_pro8: CHIP = atmega328
573
+atmega328_pro8:
574
+ $(MAKE) $(CHIP) AVR_FREQ=8000000L LED_START_FLASHES=3
575
+ mv $(PROGRAM)_$(CHIP).hex $(PROGRAM)_$(TARGET).hex
576
+ mv $(PROGRAM)_$(CHIP).lst $(PROGRAM)_$(TARGET).lst
577
+
578
+atmega328_pro8_isp: atmega328_pro8
579
+atmega328_pro8_isp: TARGET = atmega328_pro_8MHz
580
+atmega328_pro8_isp: MCU_TARGET = atmega328p
581
+# 512 byte boot, SPIEN
582
+atmega328_pro8_isp: HFUSE ?= DE
583
+# Low power xtal (16MHz) 16KCK/14CK+65ms
584
+atmega328_pro8_isp: LFUSE ?= FF
585
+# 2.7V brownout
586
+atmega328_pro8_isp: EFUSE ?= DE
587
+atmega328_pro8_isp: isp
588
+
589
+# 1MHz clocked platforms
590
+#
591
+# These are capable of 9600 baud
592
+#
593
+
594
+luminet: TARGET = luminet
595
+luminet: MCU_TARGET = attiny84
596
+luminet: CFLAGS += $(COMMON_OPTIONS) '-DSOFT_UART' '-DBAUD_RATE=9600'
597
+luminet: CFLAGS += '-DVIRTUAL_BOOT_PARTITION'
598
+luminet: AVR_FREQ ?= 1000000L
599
+luminet: LDSECTIONS = -Wl,--section-start=.text=0x1d00 -Wl,--section-start=.version=0x1efe
600
+luminet: $(PROGRAM)_luminet.hex
601
+luminet: $(PROGRAM)_luminet.lst
602
+
603
+luminet_isp: luminet
604
+luminet_isp: TARGET = luminet
605
+luminet_isp: MCU_TARGET = attiny84
606
+# Brownout disabled
607
+luminet_isp: HFUSE ?= DF
608
+# 1MHz internal oscillator, slowly rising power
609
+luminet_isp: LFUSE ?= 62
610
+# Self-programming enable
611
+luminet_isp: EFUSE ?= FE
612
+luminet_isp: isp
613
+
614
+
615
+#---------------------------------------------------------------------------
616
+#
617
+# Generic build instructions
618
+#
619
+
620
+FORCE:
621
+
622
+baudcheck: FORCE
623
+ - @$(CC) $(CFLAGS) -E baudcheck.c -o baudcheck.tmp.sh
624
+ - @sh baudcheck.tmp.sh
625
+
626
+isp: $(TARGET)
627
+ $(MAKE) -f Makefile.isp isp TARGET=$(TARGET)
628
+
629
+isp-stk500: $(PROGRAM)_$(TARGET).hex
630
+ $(STK500-1)
631
+ $(STK500-2)
632
+
633
+%.elf: $(OBJ) baudcheck $(dummy)
634
+ $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $< $(LIBS)
635
+ $(SIZE) $@
636
+
637
+clean:
638
+ rm -rf *.o *.elf *.lst *.map *.sym *.lss *.eep *.srec *.bin *.hex *.tmp.sh
639
+
640
+%.lst: %.elf
641
+ $(OBJDUMP) -h -S $< > $@
642
+
643
+%.hex: %.elf
644
+ $(OBJCOPY) -j .bootv -j .text -j .data -j .version --set-section-flags .version=alloc,load --set-section-flags .bootv=alloc,load -O ihex $< $@
645
+
646
+%.srec: %.elf
647
+ $(OBJCOPY) -j .text -j .data -j .version --set-section-flags .version=alloc,load -O srec $< $@
648
+
649
+%.bin: %.elf
650
+ $(OBJCOPY) -j .text -j .data -j .version --set-section-flags .version=alloc,load -O binary $< $@
Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/optiboot_lgt8fx8p/Makefile.isp
... ...
@@ -0,0 +1,79 @@
1
+# Makefile.isp for Optiboot
2
+# Bill Westfield ([email protected]) March, 2013
3
+# $Id$
4
+#
5
+# Instructions:
6
+#
7
+# This is a "daughter" Makefile that burns the bootloader using a ISP
8
+# device programmer. It is designed to inherit assorted variables from
9
+# the parent optiboot "Makefile"... Using a daughter makefile makes
10
+# certain variable manipulations more obvious.
11
+#
12
+# To burn bootloader .hex file, invoke the main Makefile using:
13
+# make diecimila_isp
14
+# make lilypad_isp
15
+# make ng_isp
16
+# etc...
17
+
18
+#
19
+# Note: inherit paths/etc from parent Makefile.
20
+#
21
+
22
+#---------------------------------------------------------------------------
23
+
24
+# enter the parameters for the avrdude isp tool -b19200
25
+#
26
+
27
+# Inherit avrdude paths from top-level makefile
28
+AVRDUDE_ROOT ?= $(GCCROOT)
29
+AVRDUDE_CONF ?= -C$(TOOLROOT)/avr/etc/avrdude.conf
30
+
31
+# These are the parameters for a usb-based STK500v2 programmer.
32
+# Exact type unknown. (historical Makefile values.)
33
+#ISPTOOL = stk500v2
34
+#ISPPORT = usb
35
+#ISPSPEED = -b 115200
36
+#
37
+#
38
+# These are parameters for using an Arduino with the ArduinoISP sketch
39
+# as the programmer. On a mac, for a particular Uno as programmer.
40
+ISPTOOL ?= jtag2isp
41
+ISPPORT ?= usb
42
+ISPSPEED ?= -b19200
43
+
44
+
45
+
46
+# Not all chips have EFUSE.
47
+
48
+ifdef EFUSE
49
+EFUSE_CMD= -U efuse:w:0x$(EFUSE):m
50
+endif
51
+
52
+
53
+# There are certain complicated caused by the fact that the default state
54
+# of a fuse is a "1" rather than a "0", especially with respect to fuse bits
55
+# that have not been implemented. Those would normally not be included, but
56
+# unimplemented fuses still default to being "1"
57
+#
58
+# the efuse should really be 0xf8; since, however, only the lower
59
+# three bits of that byte are used on the atmega168, avrdude gets
60
+# confused if you specify 1's for the higher bits, see:
61
+# http://tinker.it/now/2007/02/24/the-tale-of-avrdude-atmega168-and-extended-bits-fuses/
62
+#
63
+# similarly, the lock bits should be 0xff instead of 0x3f (to
64
+# unlock the bootloader section) and 0xcf instead of 0x2f (to
65
+# lock it), but since the high two bits of the lock byte are
66
+# unused, avrdude would get confused.
67
+
68
+# Set fuses and unlock memory
69
+ISPFUSES = $(AVRDUDE_ROOT)avrdude $(AVRDUDE_CONF) -c $(ISPTOOL) \
70
+ -p $(MCU_TARGET) -P $(ISPPORT) $(ISPSPEED) \
71
+ -e -u -U lock:w:0x3f:m $(EFUSE_CMD) \
72
+ -U hfuse:w:0x$(HFUSE):m -U lfuse:w:0x$(LFUSE):m
73
+# program flash and lock memory.
74
+ISPFLASH = $(AVRDUDE_ROOT)avrdude $(AVRDUDE_CONF) -c $(ISPTOOL) \
75
+ -p $(MCU_TARGET) -P $(ISPPORT) $(ISPSPEED) \
76
+ -U flash:w:$(PROGRAM)_$(TARGET).hex
77
+
78
+isp: $(PROGRAM)_$(TARGET).hex
79
+ $(ISPFLASH)
Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/optiboot_lgt8fx8p/README.TXT
... ...
@@ -0,0 +1,93 @@
1
+This directory contains the Optiboot small bootloader for AVR
2
+microcontrollers, somewhat modified specifically for the Arduino
3
+environment.
4
+
5
+Optiboot is more fully described here: http://code.google.com/p/optiboot/
6
+and is the work of Peter Knight (aka Cathedrow), building on work of Jason P
7
+Kyle, Spiff, and Ladyada. Arduino-specific modification are by Bill
8
+Westfield (aka WestfW)
9
+
10
+Arduino-specific issues are tracked as part of the Arduino project
11
+at http://code.google.com/p/arduino
12
+
13
+
14
+------------------------------------------------------------
15
+Building optiboot for Arduino.
16
+
17
+Production builds of optiboot for Arduino are done on a Mac in "unix mode"
18
+using CrossPack-AVR-20100115. CrossPack tracks WINAVR (for windows), which
19
+is just a package of avr-gcc and related utilities, so similar builds should
20
+work on Windows or Linux systems.
21
+
22
+One of the Arduino-specific changes is modifications to the makefile to
23
+allow building optiboot using only the tools installed as part of the
24
+Arduino environment, or the Arduino source development tree. All three
25
+build procedures should yield identical binaries (.hex files) (although
26
+this may change if compiler versions drift apart between CrossPack and
27
+the Arduino IDE.)
28
+
29
+
30
+Building Optiboot in the Arduino IDE Install.
31
+
32
+Work in the .../hardware/arduino/bootloaders/optiboot/ and use the
33
+"omake <targets>" command, which just generates a command that uses
34
+the arduino-included "make" utility with a command like:
35
+ make OS=windows ENV=arduino <targets>
36
+or make OS=macosx ENV=arduino <targets>
37
+On windows, this assumes you're using the windows command shell. If
38
+you're using a cygwin or mingw shell, or have one of those in your
39
+path, the build will probably break due to slash vs backslash issues.
40
+On a Mac, if you have the developer tools installed, you can use the
41
+Apple-supplied version of make.
42
+The makefile uses relative paths ("../../../tools/" and such) to find
43
+the programs it needs, so you need to work in the existing optiboot
44
+directory (or something created at the same "level") for it to work.
45
+
46
+
47
+Building Optiboot in the Arduino Source Development Install.
48
+
49
+In this case, there is no special shell script, and you're assumed to
50
+have "make" installed somewhere in your path.
51
+Build the Arduino source ("ant build") to unpack the tools into the
52
+expected directory.
53
+Work in Arduino/hardware/arduino/bootloaders/optiboot and use
54
+ make OS=windows ENV=arduinodev <targets>
55
+or make OS=macosx ENV=arduinodev <targets>
56
+
57
+
58
+Programming Chips Using the _isp Targets
59
+
60
+The CPU targets have corresponding ISP targets that will actuall
61
+program the bootloader into a chip. "atmega328_isp" for the atmega328,
62
+for example. These will set the fuses and lock bits as appropriate as
63
+well as uploading the bootloader code.
64
+
65
+ISP Targets in Version 5.0 and later:
66
+
67
+The isp targets are now built using a separate "Makefile.isp" makefile,
68
+which should make modification easier and more obvious. This also fixes
69
+the atmega8_isp target problem mentioned below. The default
70
+configuration assumes an ArduinoISP setup, but you will probably need to
71
+update at least the serial port, since those are different for each
72
+Arduino board and/or system/
73
+
74
+
75
+ISP Targets in Version 4.6 and earlier:
76
+
77
+The older makefiles default to using a USB programmer, but you can use a
78
+serial programmer like ArduinoISP by changing the appropriate variables
79
+when you invoke make:
80
+
81
+ make ISPTOOL=stk500v1 ISPPORT=/dev/tty.usbserial-A20e1eAN \
82
+ ISPSPEED=-b19200 atmega328_isp
83
+
84
+The "atmega8_isp" target does not currently work, because the mega8
85
+doesn't have the "extended" fuse that the generic ISP target wants to
86
+pass on to avrdude. You'll need to run avrdude manually.
87
+
88
+
89
+Standard Targets
90
+
91
+I've reduced the pre-built and source-version-controlled targets
92
+(.hex and .lst files included in the git repository) to just the
93
+three basic 16MHz targets: atmega8, atmega16, atmega328.
Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/optiboot_lgt8fx8p/baudcheck.c
... ...
@@ -0,0 +1,50 @@
1
+/*
2
+ * baudcheck.c
3
+ * Mar, 2013 by Bill Westfield ([email protected])
4
+ * Exercises in executing arithmetic code on a system that we can't count
5
+ * on having the usual languages or tools installed.
6
+ *
7
+ * This little "C program" is run through the C preprocessor using the same
8
+ * arguments as our "real" target (which should assure that it gets the
9
+ * same values for clock speed and desired baud rate), and produces as
10
+ * output a shell script that can be run through bash, and THAT in turn
11
+ * writes the desired output...
12
+ *
13
+ * Note that the C-style comments are stripped by the C preprocessor.
14
+ */
15
+
16
+/*
17
+ * First strip any trailing "L" from the defined constants. To do this
18
+ * we need to make the constants into shell variables first.
19
+ */
20
+bpsx=BAUD_RATE
21
+bps=${bpsx/L/}
22
+fcpux=F_CPU
23
+fcpu=${fcpux/L/}
24
+
25
+// echo f_cpu = $fcpu, baud = $bps
26
+/*
27
+ * Compute the divisor
28
+ */
29
+BAUD_SETTING=$(( ( ($fcpu + $bps * 4) / (($bps * 8))) - 1 ))
30
+// echo baud setting = $BAUD_SETTING
31
+
32
+/*
33
+ * Based on the computer divisor, calculate the actual bitrate,
34
+ * And the error. Since we're all integers, we have to calculate
35
+ * the tenths part of the error separately.
36
+ */
37
+BAUD_ACTUAL=$(( ($fcpu/(8 * (($BAUD_SETTING)+1))) ))
38
+BAUD_ERROR=$(( (( 100*($bps - $BAUD_ACTUAL) ) / $bps) ))
39
+ERR_TS=$(( ((( 1000*($bps - $BAUD_ACTUAL) ) / $bps) - $BAUD_ERROR * 10) ))
40
+ERR_TENTHS=$(( ERR_TS > 0 ? ERR_TS: -ERR_TS ))
41
+
42
+/*
43
+ * Print a nice message containing the info we've calculated
44
+ */
45
+echo BAUD RATE CHECK: Desired: $bps, Real: $BAUD_ACTUAL, UBRRL = $BAUD_SETTING, Error=$BAUD_ERROR.$ERR_TENTHS\%
46
+
47
+
48
+
49
+
50
+
Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/optiboot_lgt8fx8p/baudcheck.tmp.sh
... ...
@@ -0,0 +1,32 @@
1
+# 1 "baudcheck.c"
2
+# 1 "C:\\Users\\Administrator\\Documents\\Arduino\\hardware\\LGT\\avr\\bootloaders\\lgt8fx8p//"
3
+# 1 "<built-in>"
4
+# 1 "<command-line>"
5
+# 1 "baudcheck.c"
6
+# 20 "baudcheck.c"
7
+bpsx=57600
8
+bps=${bpsx/L/}
9
+fcpux=16000000L
10
+fcpu=${fcpux/L/}
11
+
12
+
13
+
14
+
15
+
16
+BAUD_SETTING=$(( ( ($fcpu + $bps * 4) / (($bps * 8))) - 1 ))
17
+
18
+
19
+
20
+
21
+
22
+
23
+
24
+BAUD_ACTUAL=$(( ($fcpu/(8 * (($BAUD_SETTING)+1))) ))
25
+BAUD_ERROR=$(( (( 100*($bps - $BAUD_ACTUAL) ) / $bps) ))
26
+ERR_TS=$(( ((( 1000*($bps - $BAUD_ACTUAL) ) / $bps) - $BAUD_ERROR * 10) ))
27
+ERR_TENTHS=$(( ERR_TS > 0 ? ERR_TS: -ERR_TS ))
28
+
29
+
30
+
31
+
32
+echo BAUD RATE CHECK: Desired: $bps, Real: $BAUD_ACTUAL, UBRRL = $BAUD_SETTING, Error=$BAUD_ERROR.$ERR_TENTHS\%
Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/optiboot_lgt8fx8p/boot.h
... ...
@@ -0,0 +1,848 @@
1
+/* Modified to use out for SPM access
2
+** Peter Knight, Optiboot project http://optiboot.googlecode.com
3
+**
4
+** Todo: Tidy up
5
+**
6
+** "_short" routines execute 1 cycle faster and use 1 less word of flash
7
+** by using "out" instruction instead of "sts".
8
+**
9
+** Additional elpm variants that trust the value of RAMPZ
10
+*/
11
+
12
+/* Copyright (c) 2002, 2003, 2004, 2005, 2006, 2007 Eric B. Weddington
13
+ All rights reserved.
14
+
15
+ Redistribution and use in source and binary forms, with or without
16
+ modification, are permitted provided that the following conditions are met:
17
+
18
+ * Redistributions of source code must retain the above copyright
19
+ notice, this list of conditions and the following disclaimer.
20
+ * Redistributions in binary form must reproduce the above copyright
21
+ notice, this list of conditions and the following disclaimer in
22
+ the documentation and/or other materials provided with the
23
+ distribution.
24
+ * Neither the name of the copyright holders nor the names of
25
+ contributors may be used to endorse or promote products derived
26
+ from this software without specific prior written permission.
27
+
28
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
32
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38
+ POSSIBILITY OF SUCH DAMAGE. */
39
+
40
+/* $Id: boot.h,v 1.27.2.3 2008/09/30 13:58:48 arcanum Exp $ */
41
+
42
+#ifndef _AVR_BOOT_H_
43
+#define _AVR_BOOT_H_ 1
44
+
45
+/** \file */
46
+/** \defgroup avr_boot <avr/boot.h>: Bootloader Support Utilities
47
+ \code
48
+ #include <avr/io.h>
49
+ #include <avr/boot.h>
50
+ \endcode
51
+
52
+ The macros in this module provide a C language interface to the
53
+ bootloader support functionality of certain AVR processors. These
54
+ macros are designed to work with all sizes of flash memory.
55
+
56
+ Global interrupts are not automatically disabled for these macros. It
57
+ is left up to the programmer to do this. See the code example below.
58
+ Also see the processor datasheet for caveats on having global interrupts
59
+ enabled during writing of the Flash.
60
+
61
+ \note Not all AVR processors provide bootloader support. See your
62
+ processor datasheet to see if it provides bootloader support.
63
+
64
+ \todo From email with Marek: On smaller devices (all except ATmega64/128),
65
+ __SPM_REG is in the I/O space, accessible with the shorter "in" and "out"
66
+ instructions - since the boot loader has a limited size, this could be an
67
+ important optimization.
68
+
69
+ \par API Usage Example
70
+ The following code shows typical usage of the boot API.
71
+
72
+ \code
73
+ #include <inttypes.h>
74
+ #include <avr/interrupt.h>
75
+ #include <avr/pgmspace.h>
76
+
77
+ void boot_program_page (uint32_t page, uint8_t *buf)
78
+ {
79
+ uint16_t i;
80
+ uint8_t sreg;
81
+
82
+ // Disable interrupts.
83
+
84
+ sreg = SREG;
85
+ cli();
86
+
87
+ eeprom_busy_wait ();
88
+
89
+ boot_page_erase (page);
90
+ boot_spm_busy_wait (); // Wait until the memory is erased.
91
+
92
+ for (i=0; i<SPM_PAGESIZE; i+=2)
93
+ {
94
+ // Set up little-endian word.
95
+
96
+ uint16_t w = *buf++;
97
+ w += (*buf++) << 8;
98
+
99
+ boot_page_fill (page + i, w);
100
+ }
101
+
102
+ boot_page_write (page); // Store buffer in flash page.
103
+ boot_spm_busy_wait(); // Wait until the memory is written.
104
+
105
+ // Reenable RWW-section again. We need this if we want to jump back
106
+ // to the application after bootloading.
107
+
108
+ boot_rww_enable ();
109
+
110
+ // Re-enable interrupts (if they were ever enabled).
111
+
112
+ SREG = sreg;
113
+ }\endcode */
114
+
115
+#include <avr/eeprom.h>
116
+#include <avr/io.h>
117
+#include <inttypes.h>
118
+#include <limits.h>
119
+
120
+/* Check for SPM Control Register in processor. */
121
+#if defined (SPMCSR)
122
+# define __SPM_REG SPMCSR
123
+#elif defined (SPMCR)
124
+# define __SPM_REG SPMCR
125
+#else
126
+# error AVR processor does not provide bootloader support!
127
+#endif
128
+
129
+
130
+/* Check for SPM Enable bit. */
131
+#if defined(SPMEN)
132
+# define __SPM_ENABLE SPMEN
133
+#elif defined(SELFPRGEN)
134
+# define __SPM_ENABLE SELFPRGEN
135
+#else
136
+# error Cannot find SPM Enable bit definition!
137
+#endif
138
+
139
+/** \ingroup avr_boot
140
+ \def BOOTLOADER_SECTION
141
+
142
+ Used to declare a function or variable to be placed into a
143
+ new section called .bootloader. This section and its contents
144
+ can then be relocated to any address (such as the bootloader
145
+ NRWW area) at link-time. */
146
+
147
+#define BOOTLOADER_SECTION __attribute__ ((section (".bootloader")))
148
+
149
+/* Create common bit definitions. */
150
+#ifdef ASB
151
+#define __COMMON_ASB ASB
152
+#else
153
+#define __COMMON_ASB RWWSB
154
+#endif
155
+
156
+#ifdef ASRE
157
+#define __COMMON_ASRE ASRE
158
+#else
159
+#define __COMMON_ASRE RWWSRE
160
+#endif
161
+
162
+/* Define the bit positions of the Boot Lock Bits. */
163
+
164
+#define BLB12 5
165
+#define BLB11 4
166
+#define BLB02 3
167
+#define BLB01 2
168
+
169
+/** \ingroup avr_boot
170
+ \def boot_spm_interrupt_enable()
171
+ Enable the SPM interrupt. */
172
+
173
+#define boot_spm_interrupt_enable() (__SPM_REG |= (uint8_t)_BV(SPMIE))
174
+
175
+/** \ingroup avr_boot
176
+ \def boot_spm_interrupt_disable()
177
+ Disable the SPM interrupt. */
178
+
179
+#define boot_spm_interrupt_disable() (__SPM_REG &= (uint8_t)~_BV(SPMIE))
180
+
181
+/** \ingroup avr_boot
182
+ \def boot_is_spm_interrupt()
183
+ Check if the SPM interrupt is enabled. */
184
+
185
+#define boot_is_spm_interrupt() (__SPM_REG & (uint8_t)_BV(SPMIE))
186
+
187
+/** \ingroup avr_boot
188
+ \def boot_rww_busy()
189
+ Check if the RWW section is busy. */
190
+
191
+#define boot_rww_busy() (__SPM_REG & (uint8_t)_BV(__COMMON_ASB))
192
+
193
+/** \ingroup avr_boot
194
+ \def boot_spm_busy()
195
+ Check if the SPM instruction is busy. */
196
+
197
+#define boot_spm_busy() (__SPM_REG & (uint8_t)_BV(__SPM_ENABLE))
198
+
199
+/** \ingroup avr_boot
200
+ \def boot_spm_busy_wait()
201
+ Wait while the SPM instruction is busy. */
202
+
203
+#define boot_spm_busy_wait() do{}while(boot_spm_busy())
204
+
205
+#define __BOOT_PAGE_ERASE (_BV(__SPM_ENABLE) | _BV(PGERS))
206
+#define __BOOT_PAGE_WRITE (_BV(__SPM_ENABLE) | _BV(PGWRT))
207
+#define __BOOT_PAGE_FILL _BV(__SPM_ENABLE)
208
+#define __BOOT_RWW_ENABLE (_BV(__SPM_ENABLE) | _BV(__COMMON_ASRE))
209
+#define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(BLBSET))
210
+
211
+#define __boot_page_fill_short(address, data) \
212
+(__extension__({ \
213
+ __asm__ __volatile__ \
214
+ ( \
215
+ "movw r0, %3\n\t" \
216
+ "out %0, %1\n\t" \
217
+ "spm\n\t" \
218
+ "clr r1\n\t" \
219
+ : \
220
+ : "i" (_SFR_IO_ADDR(__SPM_REG)), \
221
+ "r" ((uint8_t)__BOOT_PAGE_FILL), \
222
+ "z" ((uint16_t)address), \
223
+ "r" ((uint16_t)data) \
224
+ : "r0" \
225
+ ); \
226
+}))
227
+
228
+#define __boot_page_fill_normal(address, data) \
229
+(__extension__({ \
230
+ __asm__ __volatile__ \
231
+ ( \
232
+ "movw r0, %3\n\t" \
233
+ "sts %0, %1\n\t" \
234
+ "spm\n\t" \
235
+ "clr r1\n\t" \
236
+ : \
237
+ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
238
+ "r" ((uint8_t)__BOOT_PAGE_FILL), \
239
+ "z" ((uint16_t)address), \
240
+ "r" ((uint16_t)data) \
241
+ : "r0" \
242
+ ); \
243
+}))
244
+
245
+#define __boot_page_fill_alternate(address, data)\
246
+(__extension__({ \
247
+ __asm__ __volatile__ \
248
+ ( \
249
+ "movw r0, %3\n\t" \
250
+ "sts %0, %1\n\t" \
251
+ "spm\n\t" \
252
+ ".word 0xffff\n\t" \
253
+ "nop\n\t" \
254
+ "clr r1\n\t" \
255
+ : \
256
+ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
257
+ "r" ((uint8_t)__BOOT_PAGE_FILL), \
258
+ "z" ((uint16_t)address), \
259
+ "r" ((uint16_t)data) \
260
+ : "r0" \
261
+ ); \
262
+}))
263
+
264
+#define __boot_page_fill_extended(address, data) \
265
+(__extension__({ \
266
+ __asm__ __volatile__ \
267
+ ( \
268
+ "movw r0, %4\n\t" \
269
+ "movw r30, %A3\n\t" \
270
+ "sts %1, %C3\n\t" \
271
+ "sts %0, %2\n\t" \
272
+ "spm\n\t" \
273
+ "clr r1\n\t" \
274
+ : \
275
+ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
276
+ "i" (_SFR_MEM_ADDR(RAMPZ)), \
277
+ "r" ((uint8_t)__BOOT_PAGE_FILL), \
278
+ "r" ((uint32_t)address), \
279
+ "r" ((uint16_t)data) \
280
+ : "r0", "r30", "r31" \
281
+ ); \
282
+}))
283
+
284
+#define __boot_page_fill_extended_short(address, data) \
285
+(__extension__({ \
286
+ __asm__ __volatile__ \
287
+ ( \
288
+ "movw r0, %4\n\t" \
289
+ "movw r30, %A3\n\t" \
290
+ "out %1, %C3\n\t" \
291
+ "out %0, %2\n\t" \
292
+ "spm\n\t" \
293
+ "clr r1\n\t" \
294
+ : \
295
+ : "i" (_SFR_IO_ADDR(__SPM_REG)), \
296
+ "i" (_SFR_IO_ADDR(RAMPZ)), \
297
+ "r" ((uint8_t)__BOOT_PAGE_FILL), \
298
+ "r" ((uint32_t)address), \
299
+ "r" ((uint16_t)data) \
300
+ : "r0", "r30", "r31" \
301
+ ); \
302
+}))
303
+
304
+#define __boot_page_erase_short(address) \
305
+(__extension__({ \
306
+ __asm__ __volatile__ \
307
+ ( \
308
+ "out %0, %1\n\t" \
309
+ "spm\n\t" \
310
+ : \
311
+ : "i" (_SFR_IO_ADDR(__SPM_REG)), \
312
+ "r" ((uint8_t)__BOOT_PAGE_ERASE), \
313
+ "z" ((uint16_t)address) \
314
+ ); \
315
+}))
316
+
317
+
318
+#define __boot_page_erase_normal(address) \
319
+(__extension__({ \
320
+ __asm__ __volatile__ \
321
+ ( \
322
+ "sts %0, %1\n\t" \
323
+ "spm\n\t" \
324
+ : \
325
+ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
326
+ "r" ((uint8_t)__BOOT_PAGE_ERASE), \
327
+ "z" ((uint16_t)address) \
328
+ ); \
329
+}))
330
+
331
+#define __boot_page_erase_alternate(address) \
332
+(__extension__({ \
333
+ __asm__ __volatile__ \
334
+ ( \
335
+ "sts %0, %1\n\t" \
336
+ "spm\n\t" \
337
+ ".word 0xffff\n\t" \
338
+ "nop\n\t" \
339
+ : \
340
+ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
341
+ "r" ((uint8_t)__BOOT_PAGE_ERASE), \
342
+ "z" ((uint16_t)address) \
343
+ ); \
344
+}))
345
+
346
+#define __boot_page_erase_extended(address) \
347
+(__extension__({ \
348
+ __asm__ __volatile__ \
349
+ ( \
350
+ "movw r30, %A3\n\t" \
351
+ "sts %1, %C3\n\t" \
352
+ "sts %0, %2\n\t" \
353
+ "spm\n\t" \
354
+ : \
355
+ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
356
+ "i" (_SFR_MEM_ADDR(RAMPZ)), \
357
+ "r" ((uint8_t)__BOOT_PAGE_ERASE), \
358
+ "r" ((uint32_t)address) \
359
+ : "r30", "r31" \
360
+ ); \
361
+}))
362
+#define __boot_page_erase_extended_short(address) \
363
+(__extension__({ \
364
+ __asm__ __volatile__ \
365
+ ( \
366
+ "movw r30, %A3\n\t" \
367
+ "out %1, %C3\n\t" \
368
+ "out %0, %2\n\t" \
369
+ "spm\n\t" \
370
+ : \
371
+ : "i" (_SFR_IO_ADDR(__SPM_REG)), \
372
+ "i" (_SFR_IO_ADDR(RAMPZ)), \
373
+ "r" ((uint8_t)__BOOT_PAGE_ERASE), \
374
+ "r" ((uint32_t)address) \
375
+ : "r30", "r31" \
376
+ ); \
377
+}))
378
+
379
+#define __boot_page_write_short(address) \
380
+(__extension__({ \
381
+ __asm__ __volatile__ \
382
+ ( \
383
+ "out %0, %1\n\t" \
384
+ "spm\n\t" \
385
+ : \
386
+ : "i" (_SFR_IO_ADDR(__SPM_REG)), \
387
+ "r" ((uint8_t)__BOOT_PAGE_WRITE), \
388
+ "z" ((uint16_t)address) \
389
+ ); \
390
+}))
391
+
392
+#define __boot_page_write_normal(address) \
393
+(__extension__({ \
394
+ __asm__ __volatile__ \
395
+ ( \
396
+ "sts %0, %1\n\t" \
397
+ "spm\n\t" \
398
+ : \
399
+ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
400
+ "r" ((uint8_t)__BOOT_PAGE_WRITE), \
401
+ "z" ((uint16_t)address) \
402
+ ); \
403
+}))
404
+
405
+#define __boot_page_write_alternate(address) \
406
+(__extension__({ \
407
+ __asm__ __volatile__ \
408
+ ( \
409
+ "sts %0, %1\n\t" \
410
+ "spm\n\t" \
411
+ ".word 0xffff\n\t" \
412
+ "nop\n\t" \
413
+ : \
414
+ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
415
+ "r" ((uint8_t)__BOOT_PAGE_WRITE), \
416
+ "z" ((uint16_t)address) \
417
+ ); \
418
+}))
419
+
420
+#define __boot_page_write_extended(address) \
421
+(__extension__({ \
422
+ __asm__ __volatile__ \
423
+ ( \
424
+ "movw r30, %A3\n\t" \
425
+ "sts %1, %C3\n\t" \
426
+ "sts %0, %2\n\t" \
427
+ "spm\n\t" \
428
+ : \
429
+ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
430
+ "i" (_SFR_MEM_ADDR(RAMPZ)), \
431
+ "r" ((uint8_t)__BOOT_PAGE_WRITE), \
432
+ "r" ((uint32_t)address) \
433
+ : "r30", "r31" \
434
+ ); \
435
+}))
436
+#define __boot_page_write_extended_short(address) \
437
+(__extension__({ \
438
+ __asm__ __volatile__ \
439
+ ( \
440
+ "movw r30, %A3\n\t" \
441
+ "out %1, %C3\n\t" \
442
+ "out %0, %2\n\t" \
443
+ "spm\n\t" \
444
+ : \
445
+ : "i" (_SFR_IO_ADDR(__SPM_REG)), \
446
+ "i" (_SFR_IO_ADDR(RAMPZ)), \
447
+ "r" ((uint8_t)__BOOT_PAGE_WRITE), \
448
+ "r" ((uint32_t)address) \
449
+ : "r30", "r31" \
450
+ ); \
451
+}))
452
+
453
+#define __boot_rww_enable_short() \
454
+(__extension__({ \
455
+ __asm__ __volatile__ \
456
+ ( \
457
+ "out %0, %1\n\t" \
458
+ "spm\n\t" \
459
+ : \
460
+ : "i" (_SFR_IO_ADDR(__SPM_REG)), \
461
+ "r" ((uint8_t)__BOOT_RWW_ENABLE) \
462
+ ); \
463
+}))
464
+
465
+#define __boot_rww_enable() \
466
+(__extension__({ \
467
+ __asm__ __volatile__ \
468
+ ( \
469
+ "sts %0, %1\n\t" \
470
+ "spm\n\t" \
471
+ : \
472
+ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
473
+ "r" ((uint8_t)__BOOT_RWW_ENABLE) \
474
+ ); \
475
+}))
476
+
477
+#define __boot_rww_enable_alternate() \
478
+(__extension__({ \
479
+ __asm__ __volatile__ \
480
+ ( \
481
+ "sts %0, %1\n\t" \
482
+ "spm\n\t" \
483
+ ".word 0xffff\n\t" \
484
+ "nop\n\t" \
485
+ : \
486
+ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
487
+ "r" ((uint8_t)__BOOT_RWW_ENABLE) \
488
+ ); \
489
+}))
490
+
491
+/* From the mega16/mega128 data sheets (maybe others):
492
+
493
+ Bits by SPM To set the Boot Loader Lock bits, write the desired data to
494
+ R0, write "X0001001" to SPMCR and execute SPM within four clock cycles
495
+ after writing SPMCR. The only accessible Lock bits are the Boot Lock bits
496
+ that may prevent the Application and Boot Loader section from any
497
+ software update by the MCU.
498
+
499
+ If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit
500
+ will be programmed if an SPM instruction is executed within four cycles
501
+ after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is
502
+ don't care during this operation, but for future compatibility it is
503
+ recommended to load the Z-pointer with $0001 (same as used for reading the
504
+ Lock bits). For future compatibility It is also recommended to set bits 7,
505
+ 6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the
506
+ Lock bits the entire Flash can be read during the operation. */
507
+
508
+#define __boot_lock_bits_set_short(lock_bits) \
509
+(__extension__({ \
510
+ uint8_t value = (uint8_t)(~(lock_bits)); \
511
+ __asm__ __volatile__ \
512
+ ( \
513
+ "ldi r30, 1\n\t" \
514
+ "ldi r31, 0\n\t" \
515
+ "mov r0, %2\n\t" \
516
+ "out %0, %1\n\t" \
517
+ "spm\n\t" \
518
+ : \
519
+ : "i" (_SFR_IO_ADDR(__SPM_REG)), \
520
+ "r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
521
+ "r" (value) \
522
+ : "r0", "r30", "r31" \
523
+ ); \
524
+}))
525
+
526
+#define __boot_lock_bits_set(lock_bits) \
527
+(__extension__({ \
528
+ uint8_t value = (uint8_t)(~(lock_bits)); \
529
+ __asm__ __volatile__ \
530
+ ( \
531
+ "ldi r30, 1\n\t" \
532
+ "ldi r31, 0\n\t" \
533
+ "mov r0, %2\n\t" \
534
+ "sts %0, %1\n\t" \
535
+ "spm\n\t" \
536
+ : \
537
+ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
538
+ "r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
539
+ "r" (value) \
540
+ : "r0", "r30", "r31" \
541
+ ); \
542
+}))
543
+
544
+#define __boot_lock_bits_set_alternate(lock_bits) \
545
+(__extension__({ \
546
+ uint8_t value = (uint8_t)(~(lock_bits)); \
547
+ __asm__ __volatile__ \
548
+ ( \
549
+ "ldi r30, 1\n\t" \
550
+ "ldi r31, 0\n\t" \
551
+ "mov r0, %2\n\t" \
552
+ "sts %0, %1\n\t" \
553
+ "spm\n\t" \
554
+ ".word 0xffff\n\t" \
555
+ "nop\n\t" \
556
+ : \
557
+ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
558
+ "r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
559
+ "r" (value) \
560
+ : "r0", "r30", "r31" \
561
+ ); \
562
+}))
563
+
564
+/*
565
+ Reading lock and fuse bits:
566
+
567
+ Similarly to writing the lock bits above, set BLBSET and SPMEN (or
568
+ SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an
569
+ LPM instruction.
570
+
571
+ Z address: contents:
572
+ 0x0000 low fuse bits
573
+ 0x0001 lock bits
574
+ 0x0002 extended fuse bits
575
+ 0x0003 high fuse bits
576
+
577
+ Sounds confusing, doesn't it?
578
+
579
+ Unlike the macros in pgmspace.h, no need to care for non-enhanced
580
+ cores here as these old cores do not provide SPM support anyway.
581
+ */
582
+
583
+/** \ingroup avr_boot
584
+ \def GET_LOW_FUSE_BITS
585
+ address to read the low fuse bits, using boot_lock_fuse_bits_get
586
+ */
587
+#define GET_LOW_FUSE_BITS (0x0000)
588
+/** \ingroup avr_boot
589
+ \def GET_LOCK_BITS
590
+ address to read the lock bits, using boot_lock_fuse_bits_get
591
+ */
592
+#define GET_LOCK_BITS (0x0001)
593
+/** \ingroup avr_boot
594
+ \def GET_EXTENDED_FUSE_BITS
595
+ address to read the extended fuse bits, using boot_lock_fuse_bits_get
596
+ */
597
+#define GET_EXTENDED_FUSE_BITS (0x0002)
598
+/** \ingroup avr_boot
599
+ \def GET_HIGH_FUSE_BITS
600
+ address to read the high fuse bits, using boot_lock_fuse_bits_get
601
+ */
602
+#define GET_HIGH_FUSE_BITS (0x0003)
603
+
604
+/** \ingroup avr_boot
605
+ \def boot_lock_fuse_bits_get(address)
606
+
607
+ Read the lock or fuse bits at \c address.
608
+
609
+ Parameter \c address can be any of GET_LOW_FUSE_BITS,
610
+ GET_LOCK_BITS, GET_EXTENDED_FUSE_BITS, or GET_HIGH_FUSE_BITS.
611
+
612
+ \note The lock and fuse bits returned are the physical values,
613
+ i.e. a bit returned as 0 means the corresponding fuse or lock bit
614
+ is programmed.
615
+ */
616
+#define boot_lock_fuse_bits_get_short(address) \
617
+(__extension__({ \
618
+ uint8_t __result; \
619
+ __asm__ __volatile__ \
620
+ ( \
621
+ "ldi r30, %3\n\t" \
622
+ "ldi r31, 0\n\t" \
623
+ "out %1, %2\n\t" \
624
+ "lpm %0, Z\n\t" \
625
+ : "=r" (__result) \
626
+ : "i" (_SFR_IO_ADDR(__SPM_REG)), \
627
+ "r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
628
+ "M" (address) \
629
+ : "r0", "r30", "r31" \
630
+ ); \
631
+ __result; \
632
+}))
633
+
634
+#define boot_lock_fuse_bits_get(address) \
635
+(__extension__({ \
636
+ uint8_t __result; \
637
+ __asm__ __volatile__ \
638
+ ( \
639
+ "ldi r30, %3\n\t" \
640
+ "ldi r31, 0\n\t" \
641
+ "sts %1, %2\n\t" \
642
+ "lpm %0, Z\n\t" \
643
+ : "=r" (__result) \
644
+ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
645
+ "r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
646
+ "M" (address) \
647
+ : "r0", "r30", "r31" \
648
+ ); \
649
+ __result; \
650
+}))
651
+
652
+/** \ingroup avr_boot
653
+ \def boot_signature_byte_get(address)
654
+
655
+ Read the Signature Row byte at \c address. For some MCU types,
656
+ this function can also retrieve the factory-stored oscillator
657
+ calibration bytes.
658
+
659
+ Parameter \c address can be 0-0x1f as documented by the datasheet.
660
+ \note The values are MCU type dependent.
661
+*/
662
+
663
+#define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(SIGRD))
664
+
665
+#define boot_signature_byte_get_short(addr) \
666
+(__extension__({ \
667
+ uint16_t __addr16 = (uint16_t)(addr); \
668
+ uint8_t __result; \
669
+ __asm__ __volatile__ \
670
+ ( \
671
+ "out %1, %2\n\t" \
672
+ "lpm %0, Z" "\n\t" \
673
+ : "=r" (__result) \
674
+ : "i" (_SFR_IO_ADDR(__SPM_REG)), \
675
+ "r" ((uint8_t) __BOOT_SIGROW_READ), \
676
+ "z" (__addr16) \
677
+ ); \
678
+ __result; \
679
+}))
680
+
681
+#define boot_signature_byte_get(addr) \
682
+(__extension__({ \
683
+ uint16_t __addr16 = (uint16_t)(addr); \
684
+ uint8_t __result; \
685
+ __asm__ __volatile__ \
686
+ ( \
687
+ "sts %1, %2\n\t" \
688
+ "lpm %0, Z" "\n\t" \
689
+ : "=r" (__result) \
690
+ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
691
+ "r" ((uint8_t) __BOOT_SIGROW_READ), \
692
+ "z" (__addr16) \
693
+ ); \
694
+ __result; \
695
+}))
696
+
697
+/** \ingroup avr_boot
698
+ \def boot_page_fill(address, data)
699
+
700
+ Fill the bootloader temporary page buffer for flash
701
+ address with data word.
702
+
703
+ \note The address is a byte address. The data is a word. The AVR
704
+ writes data to the buffer a word at a time, but addresses the buffer
705
+ per byte! So, increment your address by 2 between calls, and send 2
706
+ data bytes in a word format! The LSB of the data is written to the lower
707
+ address; the MSB of the data is written to the higher address.*/
708
+
709
+/** \ingroup avr_boot
710
+ \def boot_page_erase(address)
711
+
712
+ Erase the flash page that contains address.
713
+
714
+ \note address is a byte address in flash, not a word address. */
715
+
716
+/** \ingroup avr_boot
717
+ \def boot_page_write(address)
718
+
719
+ Write the bootloader temporary page buffer
720
+ to flash page that contains address.
721
+
722
+ \note address is a byte address in flash, not a word address. */
723
+
724
+/** \ingroup avr_boot
725
+ \def boot_rww_enable()
726
+
727
+ Enable the Read-While-Write memory section. */
728
+
729
+/** \ingroup avr_boot
730
+ \def boot_lock_bits_set(lock_bits)
731
+
732
+ Set the bootloader lock bits.
733
+
734
+ \param lock_bits A mask of which Boot Loader Lock Bits to set.
735
+
736
+ \note In this context, a 'set bit' will be written to a zero value.
737
+ Note also that only BLBxx bits can be programmed by this command.
738
+
739
+ For example, to disallow the SPM instruction from writing to the Boot
740
+ Loader memory section of flash, you would use this macro as such:
741
+
742
+ \code
743
+ boot_lock_bits_set (_BV (BLB11));
744
+ \endcode
745
+
746
+ \note Like any lock bits, the Boot Loader Lock Bits, once set,
747
+ cannot be cleared again except by a chip erase which will in turn
748
+ also erase the boot loader itself. */
749
+
750
+/* Normal versions of the macros use 16-bit addresses.
751
+ Extended versions of the macros use 32-bit addresses.
752
+ Alternate versions of the macros use 16-bit addresses and require special
753
+ instruction sequences after LPM.
754
+
755
+ FLASHEND is defined in the ioXXXX.h file.
756
+ USHRT_MAX is defined in <limits.h>. */
757
+
758
+#if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \
759
+ || defined(__AVR_ATmega323__)
760
+
761
+/* Alternate: ATmega161/163/323 and 16 bit address */
762
+#define boot_page_fill(address, data) __boot_page_fill_alternate(address, data)
763
+#define boot_page_erase(address) __boot_page_erase_alternate(address)
764
+#define boot_page_write(address) __boot_page_write_alternate(address)
765
+#define boot_rww_enable() __boot_rww_enable_alternate()
766
+#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_alternate(lock_bits)
767
+
768
+#elif (FLASHEND > USHRT_MAX)
769
+
770
+/* Extended: >16 bit address */
771
+#define boot_page_fill(address, data) __boot_page_fill_extended_short(address, data)
772
+#define boot_page_erase(address) __boot_page_erase_extended_short(address)
773
+#define boot_page_write(address) __boot_page_write_extended_short(address)
774
+#define boot_rww_enable() __boot_rww_enable_short()
775
+#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_short(lock_bits)
776
+
777
+#else
778
+
779
+/* Normal: 16 bit address */
780
+#define boot_page_fill(address, data) __boot_page_fill_short(address, data)
781
+#define boot_page_erase(address) __boot_page_erase_short(address)
782
+#define boot_page_write(address) __boot_page_write_short(address)
783
+#define boot_rww_enable() __boot_rww_enable_short()
784
+#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_short(lock_bits)
785
+
786
+#endif
787
+
788
+/** \ingroup avr_boot
789
+
790
+ Same as boot_page_fill() except it waits for eeprom and spm operations to
791
+ complete before filling the page. */
792
+
793
+#define boot_page_fill_safe(address, data) \
794
+do { \
795
+ boot_spm_busy_wait(); \
796
+ eeprom_busy_wait(); \
797
+ boot_page_fill(address, data); \
798
+} while (0)
799
+
800
+/** \ingroup avr_boot
801
+
802
+ Same as boot_page_erase() except it waits for eeprom and spm operations to
803
+ complete before erasing the page. */
804
+
805
+#define boot_page_erase_safe(address) \
806
+do { \
807
+ boot_spm_busy_wait(); \
808
+ eeprom_busy_wait(); \
809
+ boot_page_erase (address); \
810
+} while (0)
811
+
812
+/** \ingroup avr_boot
813
+
814
+ Same as boot_page_write() except it waits for eeprom and spm operations to
815
+ complete before writing the page. */
816
+
817
+#define boot_page_write_safe(address) \
818
+do { \
819
+ boot_spm_busy_wait(); \
820
+ eeprom_busy_wait(); \
821
+ boot_page_write (address); \
822
+} while (0)
823
+
824
+/** \ingroup avr_boot
825
+
826
+ Same as boot_rww_enable() except waits for eeprom and spm operations to
827
+ complete before enabling the RWW mameory. */
828
+
829
+#define boot_rww_enable_safe() \
830
+do { \
831
+ boot_spm_busy_wait(); \
832
+ eeprom_busy_wait(); \
833
+ boot_rww_enable(); \
834
+} while (0)
835
+
836
+/** \ingroup avr_boot
837
+
838
+ Same as boot_lock_bits_set() except waits for eeprom and spm operations to
839
+ complete before setting the lock bits. */
840
+
841
+#define boot_lock_bits_set_safe(lock_bits) \
842
+do { \
843
+ boot_spm_busy_wait(); \
844
+ eeprom_busy_wait(); \
845
+ boot_lock_bits_set (lock_bits); \
846
+} while (0)
847
+
848
+#endif /* _AVR_BOOT_H_ */
Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/optiboot_lgt8fx8p/lgtx8p.h
... ...
@@ -0,0 +1,563 @@
1
+/*
2
+**
3
+** Copyright (c) 2013, LogicGreen techologies
4
+** All rights reserved.
5
+**
6
+** project : LGT8F328PBSPPrj
7
+** filename : lgt8f328p_spec.h
8
+** version : 1.0
9
+** date : Feb 01, 2017
10
+
11
+VERSION HISTORY:
12
+----------------
13
+Version : 1.0
14
+Date : Feb 01, 2017
15
+Revised by : LogicGreen Software Group
16
+Description : Original version.
17
+**
18
+*/
19
+
20
+#ifndef _LGT8F328P_SPEC_H_
21
+#define _LGT8F328P_SPEC_H_
22
+
23
+//----------------------------------------------------------------
24
+// DSU (Digital Signal Co-processor) Register Definition
25
+//----------------------------------------------------------------
26
+#define DSCR (*((volatile unsigned char *)0x20))
27
+#define DSUEN 7
28
+#define MM 6
29
+#define DSD1 5
30
+#define DSD0 4
31
+#define DSN 2
32
+#define DSZ 1
33
+#define DSC 0
34
+
35
+#define DSIR (*((volatile unsigned char *)0x21))
36
+#define DSSD (*((volatile unsigned char *)0x22))
37
+
38
+#define DSDX (*((volatile unsigned char *)0x30))
39
+#define DSDY (*((volatile unsigned char *)0x31))
40
+
41
+#define DSAL (*((volatile unsigned char *)0x58))
42
+#define DSAH (*((volatile unsigned char *)0x59))
43
+
44
+//----------------------------------------------------------------
45
+// GPIO Group C Register Definition
46
+//----------------------------------------------------------------
47
+#define PC7 7
48
+
49
+//----------------------------------------------------------------
50
+// GPIO Group E Register Definition
51
+//----------------------------------------------------------------
52
+#define IPINE (*((volatile unsigned char *)0x2C))
53
+#define IDDRE (*((volatile unsigned char *)0x2D))
54
+#define IPORTE (*((volatile unsigned char *)0x2E))
55
+
56
+#define EPINE (*((volatile unsigned char *)0xA7))
57
+#define EDDRE (*((volatile unsigned char *)0xA8))
58
+#define EPORTE (*((volatile unsigned char *)0xA9))
59
+
60
+//#define USE_EIO_EREG
61
+
62
+#ifdef USE_EIO_EREG
63
+#define PINE EPINE
64
+#define DDRE EDDRE
65
+#define PORTE EPORTE
66
+#else
67
+#define PINE IPINE
68
+#define DDRE IDDRE
69
+#define PORTE IPORTE
70
+#endif
71
+
72
+#define OCPUE (*((volatile unsigned char *)0xE1))
73
+
74
+#define PE7 7
75
+#define PE6 6
76
+#define PE5 5
77
+#define PE4 4
78
+#define PE3 3
79
+#define PE2 2
80
+#define PE1 1
81
+#define PE0 0
82
+
83
+//----------------------------------------------------------------
84
+// GPIO Group F Register Definition
85
+//----------------------------------------------------------------
86
+#define PINF (*((volatile unsigned char *)0x32))
87
+#define DDRF (*((volatile unsigned char *)0x33))
88
+#define PORTF (*((volatile unsigned char *)0x34))
89
+
90
+#define PF7 7
91
+#define PF6 6
92
+#define PF5 5
93
+#define PF4 4
94
+#define PF3 3
95
+#define PF2 2
96
+#define PF1 1
97
+#define PF0 0
98
+
99
+//----------------------------------------------------------------
100
+// SPI (Serial Periphral Interface) Register Definition
101
+//----------------------------------------------------------------
102
+#define SPFR (*((volatile unsigned char *)0x39))
103
+#define RDFULL 7
104
+#define RDEMPT 6
105
+#define RDPTR1 5
106
+#define RDPTR0 4
107
+#define WRFULL 3
108
+#define WREMPT 2
109
+#define WRPTR1 1
110
+#define WRPTR0 0
111
+
112
+// Bits of SPSR
113
+#define DUAL 2
114
+
115
+//----------------------------------------------------------------
116
+// AC0 (Analog Comparator 0) Register Definition
117
+//----------------------------------------------------------------
118
+#define C0SR (*((volatile unsigned char *)0x50))
119
+#define C0D 7
120
+#define C0BG 6
121
+#define C0O 5
122
+#define C0I 4
123
+#define C0IE 3
124
+#define C0IC 2
125
+#define C0IS1 1
126
+#define C0IS0 0
127
+
128
+#define C0XR (*((volatile unsigned char *)0x51))
129
+#define C0OE 6
130
+#define C0HSYE 5
131
+#define C0PS0 4
132
+#define C0WKE 3
133
+#define C0FEN 2
134
+#define C0FS1 1
135
+#define C0FS0 0
136
+
137
+#define C0TR (*((volatile unsigned char *)0x52))
138
+
139
+//----------------------------------------------------------------
140
+// AC1 (Analog Comparator 1) Register Definition
141
+//----------------------------------------------------------------
142
+#define C1SR (*((volatile unsigned char *)0x2F))
143
+#define C1D 7
144
+#define C1BG 6
145
+#define C1O 5
146
+#define C1I 4
147
+#define C1IE 3
148
+#define C1IC 2
149
+#define C1IS1 1
150
+#define C1IS0 0
151
+
152
+#define C1XR (*((volatile unsigned char *)0x3A))
153
+#define C1OE 6
154
+#define C1HSYE 5
155
+#define C1PS0 4
156
+#define C1WKE 3
157
+#define C1FEN 2
158
+#define C1FS1 1
159
+#define C1FS0 0
160
+
161
+#define C1TR (*((volatile unsigned char *)0x5B))
162
+
163
+//----------------------------------------------------------------
164
+// EEP (E2PROM Controller) Register Definition
165
+//----------------------------------------------------------------
166
+#define E2PDL (*((volatile unsigned char *)0x40))
167
+#define E2PDH (*((volatile unsigned char *)0x5A))
168
+
169
+#define E2PD0 (*((volatile unsigned char *)0x40))
170
+#define E2PD1 (*((volatile unsigned char *)0x5A))
171
+#define E2PD2 (*((volatile unsigned char *)0x57))
172
+#define E2PD3 (*((volatile unsigned char *)0x5C))
173
+
174
+#define ECCR (*((volatile unsigned char *)0x56))
175
+#define ECS 0
176
+#define CP0 2
177
+#define CP1 3
178
+#define SWM 4
179
+#define ERN 5
180
+#define EEN 6
181
+#define EWEN 7
182
+
183
+//----------------------------------------------------------------
184
+// TC0 (Timer Counter 0) Register Definition
185
+//----------------------------------------------------------------
186
+#define TCCR0C (*((volatile unsigned char *)0x49))
187
+#define DSX07 7
188
+#define DSX06 6
189
+#define DSX05 5
190
+#define DSX04 4
191
+#define DSX01 1
192
+#define DSX00 0
193
+
194
+#define DTR0 (*((volatile unsigned char *)0x4F))
195
+
196
+// Bits of TCCR0B
197
+#define OC0AS 5
198
+#define DTEN0 4
199
+
200
+// Bits of TIFR0
201
+#define OC0A 7
202
+#define OC0B 6
203
+
204
+//----------------------------------------------------------------
205
+// TC1 (Timer Counter 1) Register Definition
206
+//----------------------------------------------------------------
207
+#define TCCR1D (*((volatile unsigned char *)0x83))
208
+#define DSX17 7
209
+#define DSX16 6
210
+#define DSX15 5
211
+#define DSX14 4
212
+#define DSX11 1
213
+#define DSX10 0
214
+
215
+#define DTR1L (*((volatile unsigned char *)0x8C))
216
+#define DTR1H (*((volatile unsigned char *)0x8D))
217
+
218
+#define PSSR (*((volatile unsigned char *)0xE2))
219
+#define PSS1 7
220
+#define PSR1 0
221
+
222
+#define TCKSR (*((volatile unsigned char *)0xEC))
223
+#define TCKCSR (*((volatile unsigned char *)0xEC))
224
+#define F2XEN 6
225
+#define TC2XF1 5
226
+#define TC2XF0 4
227
+#define TC2XS1 1
228
+#define TC2XS0 0
229
+
230
+// Bits of TCCR1C
231
+#define DOC1B 5
232
+#define DOC1A 4
233
+#define DTEN1 3
234
+
235
+// Bits of TIFR1
236
+#define OC1A 7
237
+#define OC1B 6
238
+
239
+//----------------------------------------------------------------
240
+// TC2 (Timer Counter 2) Register Definition
241
+//----------------------------------------------------------------
242
+
243
+// Bits of ASSR
244
+#define INTCK 7
245
+
246
+// Bits of TIFR2
247
+#define OC2A 7
248
+#define OC2B 6
249
+
250
+//----------------------------------------------------------------
251
+// TC3 (Timer Counter 3) Register Definition
252
+//----------------------------------------------------------------
253
+#define TIFR3 (*((volatile unsigned char *)0x38))
254
+#define OC3A 7
255
+#define OC3B 6
256
+#define ICF3 5
257
+#define OCF3C 3
258
+#define OCF3B 2
259
+#define OCF3A 1
260
+#define TOV3 0
261
+
262
+#define TIMSK3 (*((volatile unsigned char *)0x71))
263
+#define ICIE3 5
264
+#define OCIE3C 3
265
+#define OCIE3B 2
266
+#define OCIE3A 1
267
+#define TOIE3 0
268
+
269
+#define TCCR3A (*((volatile unsigned char *)0x90))
270
+#define COM3A1 7
271
+#define COM3A0 6
272
+#define COM3B1 5
273
+#define COM3B0 4
274
+#define COM3C1 3
275
+#define COM3C0 2
276
+#define WGM31 1
277
+#define WGM30 0
278
+
279
+#define TCCR3B (*((volatile unsigned char *)0x91))
280
+#define ICNC3 7
281
+#define ICES3 6
282
+#define WGM33 4
283
+#define WGM32 3
284
+#define CS32 2
285
+#define CS31 1
286
+#define CS30 0
287
+
288
+#define TCCR3C (*((volatile unsigned char *)0x92))
289
+#define FOC3A 7
290
+#define FOC3B 6
291
+#define DOC31 5
292
+#define DOC30 4
293
+#define DTEN3 3
294
+#define DOC32 1
295
+#define FOC3C 0
296
+
297
+#define TCCR3D (*((volatile unsigned char *)0x93))
298
+#define DSX37 7
299
+#define DSX36 6
300
+#define DSX35 5
301
+#define DSX34 4
302
+#define DSX31 1
303
+#define DSX30 0
304
+
305
+#define TCNT3L (*((volatile unsigned char *)0x94))
306
+#define TCNT3H (*((volatile unsigned char *)0x95))
307
+
308
+#define ICR3L (*((volatile unsigned char *)0x96))
309
+#define ICR3H (*((volatile unsigned char *)0x97))
310
+
311
+#define OCR3AL (*((volatile unsigned char *)0x98))
312
+#define OCR3AH (*((volatile unsigned char *)0x99))
313
+
314
+#define OCR3BL (*((volatile unsigned char *)0x9A))
315
+#define OCR3BH (*((volatile unsigned char *)0x9B))
316
+
317
+#define DTR3A (*((volatile unsigned char *)0x9C))
318
+#define DTR3B (*((volatile unsigned char *)0x9D))
319
+
320
+#define OCR3CL (*((volatile unsigned char *)0x9E))
321
+#define OCR3CH (*((volatile unsigned char *)0x9F))
322
+
323
+// Bits of PSSR
324
+#define PSS3 6
325
+#define PSR3 1
326
+
327
+//----------------------------------------------------------------
328
+// PCI (PIN Change Interrupt) Register Definition
329
+//----------------------------------------------------------------
330
+#define PCMSK3 (*((volatile unsigned char *)0x73))
331
+#define PCMSK4 (*((volatile unsigned char *)0x74))
332
+
333
+// Bits of PCICR
334
+#define PCIE4 4
335
+#define PCIE3 3
336
+
337
+// Bits of PCIFR
338
+#define PCIF4 4
339
+#define PCIF3 3
340
+
341
+//----------------------------------------------------------------
342
+// ADC (Analog to Digital Controller) Register Definition
343
+//----------------------------------------------------------------
344
+
345
+// bit of ADCSRB
346
+#define ICTL 4
347
+
348
+#define ADCSRC (*((volatile unsigned char *)0x7D))
349
+#define OFEN 7
350
+#define OFSF 6
351
+#define SPN 5
352
+#define AMEN 4
353
+#define SPD 2
354
+#define DIFS 1
355
+#define ADTM 0
356
+
357
+#define OFR0 (*((volatile unsigned char *)0xA3))
358
+#define OFR1 (*((volatile unsigned char *)0xA4))
359
+
360
+#define ADT0L (*((volatile unsigned char *)0xA5))
361
+#define ADT0H (*((volatile unsigned char *)0xA6))
362
+
363
+#define ADT1L (*((volatile unsigned char *)0xAA))
364
+#define ADT1H (*((volatile unsigned char *)0xAB))
365
+
366
+#define ADMSC (*((volatile unsigned char *)0xAC))
367
+#define AMOF 7
368
+#define AMFC3 3
369
+#define AMFC2 2
370
+#define AMFC1 1
371
+#define AMFC0 0
372
+
373
+#define ADCSRD (*((volatile unsigned char *)0xAD))
374
+#define BGEN 7
375
+#define REFS2 6
376
+#define IVSEL1 5
377
+#define IVSEL0 4
378
+#define VDS2 2
379
+#define VDS1 1
380
+#define VDS0 0
381
+
382
+#define DAPCR (*((volatile unsigned char *)0xDC))
383
+#define DAPEN 7
384
+#define GA1 6
385
+#define GA0 5
386
+#define DNS2 4
387
+#define DNS1 3
388
+#define DNS0 2
389
+#define DPS1 1
390
+#define DPS0 0
391
+
392
+#define DAPTR (*((volatile unsigned char *)0xDD))
393
+
394
+#define DAPTC (*((volatile unsigned char *)0xDE))
395
+#define DAPTE 7
396
+
397
+// Bits of ADCSRB
398
+#define ACME01 7
399
+#define ACME00 6
400
+#define ACME11 5
401
+#define ACME10 4
402
+#define ACTS 3
403
+
404
+// Bits of DIDR0
405
+#define ADC7D 7
406
+#define ADC6D 6
407
+#define PE3D 7
408
+#define PE1D 6
409
+#define PC5D 5
410
+#define PC4D 4
411
+#define PC3D 3
412
+#define PC2D 2
413
+#define PC1D 1
414
+#define PC0D 0
415
+
416
+// Bits of DIDR1
417
+#define PE7D 7
418
+#define PE6D 6
419
+#define PE0D 5
420
+#define C0PD 4
421
+#define PF0D 3
422
+#define PC7D 2
423
+#define PD7D 1
424
+#define PD6D 0
425
+
426
+#define DIDR2 (*((volatile unsigned char *)0x76))
427
+#define PB5D 6
428
+
429
+//----------------------------------------------------------------
430
+// DAC (Digital to Analog Controller) Register Definition
431
+//----------------------------------------------------------------
432
+#define DACON (*((volatile unsigned char *)0xA0))
433
+#define DACEN 3
434
+#define DAOE 2
435
+#define DAVS1 1
436
+#define DAVS0 0
437
+
438
+#define DALR (*((volatile unsigned char *)0xA1))
439
+
440
+//----------------------------------------------------------------
441
+// Config () Register Definition
442
+//----------------------------------------------------------------
443
+// Bits of MCUCR
444
+#define FWKEN 7
445
+#define FPDEN 6
446
+#define EXRFD 5
447
+#define IRLD 3
448
+#define IFAIL 2
449
+#define MWCE 0
450
+
451
+// Bits of MCUSR
452
+#define SWDD 7
453
+#define OCDRF 4
454
+
455
+// Bits of CLKPR
456
+#define WCE 7
457
+#define CLKOE1 6
458
+#define CLKOE0 5
459
+#define CLKOE 5
460
+
461
+#define VDTCR (*((volatile unsigned char *)0x62))
462
+//#define WCE 7
463
+#define SWR 6
464
+#define VDTS2 4
465
+#define VDTS1 3
466
+#define VDTS0 2
467
+#define VDREN 1
468
+#define VDTEN 0
469
+
470
+#define PRR1 (*((volatile unsigned char *)0x65))
471
+#define PRWDT 5
472
+#define PRTC3 3
473
+#define PREFL 2
474
+#define PRPCI 1
475
+
476
+#define RCMCAL (*((volatile unsigned char *)0x66))
477
+#define RCKCAL (*((volatile unsigned char *)0x67))
478
+
479
+#define IVBASE (*((volatile unsigned char *)0x75))
480
+
481
+#define IOCWK (*((volatile unsigned char *)0xAE))
482
+#define IOCD7
483
+#define IOCD6
484
+#define IOCD5
485
+#define IOCD4
486
+#define IOCD3
487
+#define IOCD2
488
+#define IOCD1
489
+#define IOCD0
490
+
491
+#define DPS2R (*((volatile unsigned char *)0xAF))
492
+#define DPS2E 3
493
+#define LPRCE 2
494
+#define TOS1 1
495
+#define TOS0 0
496
+
497
+#define VCAL (*((volatile unsigned char *)0xC8))
498
+#define VCAL3 (*((volatile unsigned char *)0xCC))
499
+#define VCAL1 (*((volatile unsigned char *)0xCD))
500
+#define VCAL2 (*((volatile unsigned char *)0xCE))
501
+
502
+#define LDOCR (*((volatile unsigned char *)0xCF))
503
+//#define WCE 7
504
+#define PDEN 3
505
+#define VSEL2 2
506
+#define VSEL1 1
507
+#define VSEL0 0
508
+
509
+#define HDR (*((volatile unsigned char *)0xE0))
510
+#define HDR5 5
511
+#define HDR4 4
512
+#define HDR3 3
513
+#define HDR2 2
514
+#define HDR1 1
515
+#define HDR0 0
516
+
517
+#define PMX1 (*((volatile unsigned char *)0xED))
518
+#define C3AC 2
519
+#define C2BF7 1
520
+#define C2AF6 0
521
+
522
+#define PMX0 (*((volatile unsigned char *)0xEE))
523
+//#define WCE 7
524
+#define C1BF4 6
525
+#define C1AF5 5
526
+#define C0BF3 4
527
+#define C0AC0 3
528
+#define SSB1 2
529
+#define TXD6 1
530
+#define RXD5 0
531
+
532
+#define PMX2 (*((volatile unsigned char *)0xF0))
533
+#define IOCR (*((volatile unsigned char *)0xF0))
534
+//#define WCE 7
535
+#define IOCE 7
536
+#define STSC1 6
537
+#define STSC0 5
538
+#define XIEN 2
539
+#define E6EN 1
540
+#define REFIOEN 1
541
+#define C6EN 0
542
+#define RSTIOEN 0
543
+
544
+#define PMCR (*((volatile unsigned char *)0xF2))
545
+#define PMCE 7
546
+#define CLKFS 6
547
+#define CLKSS 5
548
+#define WCLKS 4
549
+#define WCES 4
550
+#define OSCKEN 3
551
+#define OSCMEN 2
552
+#define RCKEN 1
553
+#define RCMEN 0
554
+
555
+#define GUID0 (*((volatile unsigned char *)0xF3))
556
+#define GUID1 (*((volatile unsigned char *)0xF4))
557
+#define GUID2 (*((volatile unsigned char *)0xF5))
558
+#define GUID3 (*((volatile unsigned char *)0xF6))
559
+
560
+#endif
561
+/**********************************************************************************
562
+*** EOF ***
563
+**********************************************************************************/
Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/optiboot_lgt8fx8p/optiboot.c
... ...
@@ -0,0 +1,879 @@
1
+/**********************************************************/
2
+/* Optiboot bootloader for Arduino */
3
+/* */
4
+/* http://optiboot.googlecode.com */
5
+/* */
6
+/* Arduino-maintained version : See README.TXT */
7
+/* http://code.google.com/p/arduino/ */
8
+/* It is the intent that changes not relevant to the */
9
+/* Arduino production envionment get moved from the */
10
+/* optiboot project to the arduino project in "lumps." */
11
+/* */
12
+/* Heavily optimised bootloader that is faster and */
13
+/* smaller than the Arduino standard bootloader */
14
+/* */
15
+/* Enhancements: */
16
+/* Fits in 512 bytes, saving 1.5K of code space */
17
+/* Background page erasing speeds up programming */
18
+/* Higher baud rate speeds up programming */
19
+/* Written almost entirely in C */
20
+/* Customisable timeout with accurate timeconstant */
21
+/* Optional virtual UART. No hardware UART required. */
22
+/* Optional virtual boot partition for devices without. */
23
+/* */
24
+/* What you lose: */
25
+/* Implements a skeleton STK500 protocol which is */
26
+/* missing several features including EEPROM */
27
+/* programming and non-page-aligned writes */
28
+/* High baud rate breaks compatibility with standard */
29
+/* Arduino flash settings */
30
+/* */
31
+/* Fully supported: */
32
+/* ATmega168 based devices (Diecimila etc) */
33
+/* ATmega328P based devices (Duemilanove etc) */
34
+/* */
35
+/* Beta test (believed working.) */
36
+/* ATmega8 based devices (Arduino legacy) */
37
+/* ATmega328 non-picopower devices */
38
+/* ATmega644P based devices (Sanguino) */
39
+/* ATmega1284P based devices */
40
+/* ATmega1280 based devices (Arduino Mega) */
41
+/* */
42
+/* Alpha test */
43
+/* ATmega32 */
44
+/* */
45
+/* Work in progress: */
46
+/* ATtiny84 based devices (Luminet) */
47
+/* */
48
+/* Does not support: */
49
+/* USB based devices (eg. Teensy, Leonardo) */
50
+/* */
51
+/* Assumptions: */
52
+/* The code makes several assumptions that reduce the */
53
+/* code size. They are all true after a hardware reset, */
54
+/* but may not be true if the bootloader is called by */
55
+/* other means or on other hardware. */
56
+/* No interrupts can occur */
57
+/* UART and Timer 1 are set to their reset state */
58
+/* SP points to RAMEND */
59
+/* */
60
+/* Code builds on code, libraries and optimisations from: */
61
+/* stk500boot.c by Jason P. Kyle */
62
+/* Arduino bootloader http://arduino.cc */
63
+/* Spiff's 1K bootloader http://spiffie.org/know/arduino_1k_bootloader/bootloader.shtml */
64
+/* avr-libc project http://nongnu.org/avr-libc */
65
+/* Adaboot http://www.ladyada.net/library/arduino/bootloader.html */
66
+/* AVR305 Atmel Application Note */
67
+/* */
68
+/* This program is free software; you can redistribute it */
69
+/* and/or modify it under the terms of the GNU General */
70
+/* Public License as published by the Free Software */
71
+/* Foundation; either version 2 of the License, or */
72
+/* (at your option) any later version. */
73
+/* */
74
+/* This program is distributed in the hope that it will */
75
+/* be useful, but WITHOUT ANY WARRANTY; without even the */
76
+/* implied warranty of MERCHANTABILITY or FITNESS FOR A */
77
+/* PARTICULAR PURPOSE. See the GNU General Public */
78
+/* License for more details. */
79
+/* */
80
+/* You should have received a copy of the GNU General */
81
+/* Public License along with this program; if not, write */
82
+/* to the Free Software Foundation, Inc., */
83
+/* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
84
+/* */
85
+/* Licence can be viewed at */
86
+/* http://www.fsf.org/licenses/gpl.txt */
87
+/* */
88
+/**********************************************************/
89
+
90
+
91
+/**********************************************************/
92
+/* */
93
+/* Optional defines: */
94
+/* */
95
+/**********************************************************/
96
+/* */
97
+/* BIG_BOOT: */
98
+/* Build a 1k bootloader, not 512 bytes. This turns on */
99
+/* extra functionality. */
100
+/* */
101
+/* BAUD_RATE: */
102
+/* Set bootloader baud rate. */
103
+/* */
104
+/* LUDICROUS_SPEED: */
105
+/* 230400 baud :-) */
106
+/* */
107
+/* SOFT_UART: */
108
+/* Use AVR305 soft-UART instead of hardware UART. */
109
+/* */
110
+/* LED_START_FLASHES: */
111
+/* Number of LED flashes on bootup. */
112
+/* */
113
+/* LED_DATA_FLASH: */
114
+/* Flash LED when transferring data. For boards without */
115
+/* TX or RX LEDs, or for people who like blinky lights. */
116
+/* */
117
+/* SUPPORT_EEPROM: */
118
+/* Support reading and writing from EEPROM. This is not */
119
+/* used by Arduino, so off by default. */
120
+/* */
121
+/* TIMEOUT_MS: */
122
+/* Bootloader timeout period, in milliseconds. */
123
+/* 500,1000,2000,4000,8000 supported. */
124
+/* */
125
+/* UART: */
126
+/* UART number (0..n) for devices with more than */
127
+/* one hardware uart (644P, 1284P, etc) */
128
+/* */
129
+/**********************************************************/
130
+
131
+/**********************************************************/
132
+/* Version Numbers! */
133
+/* */
134
+/* Arduino Optiboot now includes this Version number in */
135
+/* the source and object code. */
136
+/* */
137
+/* Version 3 was released as zip from the optiboot */
138
+/* repository and was distributed with Arduino 0022. */
139
+/* Version 4 starts with the arduino repository commit */
140
+/* that brought the arduino repository up-to-date with */
141
+/* the optiboot source tree changes since v3. */
142
+/* Version 5 was created at the time of the new Makefile */
143
+/* structure (Mar, 2013), even though no binaries changed*/
144
+/* It would be good if versions implemented outside the */
145
+/* official repository used an out-of-seqeunce version */
146
+/* number (like 104.6 if based on based on 4.5) to */
147
+/* prevent collisions. */
148
+/* */
149
+/**********************************************************/
150
+
151
+/**********************************************************/
152
+/* Edit History: */
153
+/* */
154
+/* Mar 2013 */
155
+/* 5.0 WestfW: Major Makefile restructuring. */
156
+/* See Makefile and pin_defs.h */
157
+/* (no binary changes) */
158
+/* */
159
+/* 4.6 WestfW/Pito: Add ATmega32 support */
160
+/* 4.6 WestfW/radoni: Don't set LED_PIN as an output if */
161
+/* not used. (LED_START_FLASHES = 0) */
162
+/* Jan 2013 */
163
+/* 4.6 WestfW/dkinzer: use autoincrement lpm for read */
164
+/* 4.6 WestfW/dkinzer: pass reset cause to app in R2 */
165
+/* Mar 2012 */
166
+/* 4.5 WestfW: add infrastructure for non-zero UARTS. */
167
+/* 4.5 WestfW: fix SIGNATURE_2 for m644 (bad in avr-libc) */
168
+/* Jan 2012: */
169
+/* 4.5 WestfW: fix NRWW value for m1284. */
170
+/* 4.4 WestfW: use attribute OS_main instead of naked for */
171
+/* main(). This allows optimizations that we */
172
+/* count on, which are prohibited in naked */
173
+/* functions due to PR42240. (keeps us less */
174
+/* than 512 bytes when compiler is gcc4.5 */
175
+/* (code from 4.3.2 remains the same.) */
176
+/* 4.4 WestfW and Maniacbug: Add m1284 support. This */
177
+/* does not change the 328 binary, so the */
178
+/* version number didn't change either. (?) */
179
+/* June 2011: */
180
+/* 4.4 WestfW: remove automatic soft_uart detect (didn't */
181
+/* know what it was doing or why.) Added a */
182
+/* check of the calculated BRG value instead. */
183
+/* Version stays 4.4; existing binaries are */
184
+/* not changed. */
185
+/* 4.4 WestfW: add initialization of address to keep */
186
+/* the compiler happy. Change SC'ed targets. */
187
+/* Return the SW version via READ PARAM */
188
+/* 4.3 WestfW: catch framing errors in getch(), so that */
189
+/* AVRISP works without HW kludges. */
190
+/* http://code.google.com/p/arduino/issues/detail?id=368n*/
191
+/* 4.2 WestfW: reduce code size, fix timeouts, change */
192
+/* verifySpace to use WDT instead of appstart */
193
+/* 4.1 WestfW: put version number in binary. */
194
+/**********************************************************/
195
+
196
+#define OPTIBOOT_MAJVER 5
197
+#define OPTIBOOT_MINVER 0
198
+
199
+#define MAKESTR(a) #a
200
+#define MAKEVER(a, b) MAKESTR(a*256+b)
201
+
202
+#if defined (__AVR_ATmega328__) || defined(__AVR_ATmega328P__)
203
+// boot_code : jmp to 0x7400 (start of bootloader)
204
+asm(" .section .bootv\n"
205
+ "boot_code: .word 0x940c\n"
206
+ ".word 0x3a00\n");
207
+#else
208
+#if #defined(__AVR_ATmega168__)
209
+// boot_code : jmp to 0x3c00 (start of bootloader)
210
+asm(" .section .bootv\n"
211
+ "boot_code: .word 0x940c\n"
212
+ ".word 0x1e00\n");
213
+#endif
214
+#endif
215
+
216
+asm(" .section .version\n"
217
+ "optiboot_version: .word " MAKEVER(OPTIBOOT_MAJVER, OPTIBOOT_MINVER) "\n"
218
+ " .section .text\n");
219
+
220
+#include <inttypes.h>
221
+#include <avr/io.h>
222
+
223
+// We don't use <avr/wdt.h> as those routines have interrupt overhead we don't need.
224
+
225
+#include "pin_defs.h"
226
+#include "stk500.h"
227
+#include "lgtx8p.h"
228
+
229
+typedef union {
230
+ uint32_t dword;
231
+ uint8_t byte[4];
232
+} *pdword_t, dword_t;
233
+
234
+#ifndef LED_START_FLASHES
235
+#define LED_START_FLASHES 0
236
+#endif
237
+
238
+#ifdef LUDICROUS_SPEED
239
+#define BAUD_RATE 230400L
240
+#endif
241
+
242
+/* set the UART baud rate defaults */
243
+#ifndef BAUD_RATE
244
+#if F_CPU >= 8000000L
245
+#define BAUD_RATE 115200L // Highest rate Avrdude win32 will support
246
+#elif F_CPU >= 1000000L
247
+#define BAUD_RATE 9600L // 19200 also supported, but with significant error
248
+#elif F_CPU >= 128000L
249
+#define BAUD_RATE 4800L // Good for 128kHz internal RC
250
+#else
251
+#define BAUD_RATE 1200L // Good even at 32768Hz
252
+#endif
253
+#endif
254
+
255
+#ifndef UART
256
+#define UART 0
257
+#endif
258
+
259
+#define BAUD_SETTING (( (F_CPU + BAUD_RATE * 4L) / ((BAUD_RATE * 8L))) - 1 )
260
+#define BAUD_ACTUAL (F_CPU/(8 * ((BAUD_SETTING)+1)))
261
+#define BAUD_ERROR (( 100*(BAUD_RATE - BAUD_ACTUAL) ) / BAUD_RATE)
262
+
263
+#if BAUD_ERROR >= 5
264
+#error BAUD_RATE error greater than 5%
265
+#elif BAUD_ERROR <= -5
266
+#error BAUD_RATE error greater than -5%
267
+#elif BAUD_ERROR >= 2
268
+#warning BAUD_RATE error greater than 2%
269
+#elif BAUD_ERROR <= -2
270
+#warning BAUD_RATE error greater than -2%
271
+#endif
272
+
273
+#if 0
274
+/* Switch in soft UART for hard baud rates */
275
+/*
276
+ * I don't understand what this was supposed to accomplish, where the
277
+ * constant "280" came from, or why automatically (and perhaps unexpectedly)
278
+ * switching to a soft uart is a good thing, so I'm undoing this in favor
279
+ * of a range check using the same calc used to config the BRG...
280
+ */
281
+#if (F_CPU/BAUD_RATE) > 280 // > 57600 for 16MHz
282
+#ifndef SOFT_UART
283
+#define SOFT_UART
284
+#endif
285
+#endif
286
+#else // 0
287
+#if (F_CPU + BAUD_RATE * 4L) / (BAUD_RATE * 8L) - 1 > 250
288
+#error Unachievable baud rate (too slow) BAUD_RATE
289
+#endif // baud rate slow check
290
+#if (F_CPU + BAUD_RATE * 4L) / (BAUD_RATE * 8L) - 1 < 3
291
+#error Unachievable baud rate (too fast) BAUD_RATE
292
+#endif // baud rate fastn check
293
+#endif
294
+
295
+/* Watchdog settings */
296
+#define WATCHDOG_OFF (0)
297
+#define WATCHDOG_1MS (_BV(WDE))
298
+#define WATCHDOG_2MS (_BV(WDP0) | _BV(WDE))
299
+#define WATCHDOG_4MS (_BV(WDP1) | _BV(WDE))
300
+#define WATCHDOG_8MS (_BV(WDP1) | _BV(WDP0) | _BV(WDE))
301
+#define WATCHDOG_16MS (_BV(WDP2) | _BV(WDE))
302
+#define WATCHDOG_32MS (_BV(WDP2) | _BV(WDP0) | _BV(WDE))
303
+#define WATCHDOG_64MS (_BV(WDP2) | _BV(WDP1) | _BV(WDE))
304
+#define WATCHDOG_128MS (_BV(WDP2) | _BV(WDP1) | _BV(WDP0) | _BV(WDE))
305
+#define WATCHDOG_256MS (_BV(WDP3) | _BV(WDE))
306
+#define WATCHDOG_512MS (_BV(WDP3) | _BV(WDP0) | _BV(WDE))
307
+
308
+/* Function Prototypes */
309
+/* The main function is in init9, which removes the interrupt vector table */
310
+/* we don't need. It is also 'naked', which means the compiler does not */
311
+/* generate any entry or exit code itself. */
312
+int main(void) __attribute__ ((OS_main)) __attribute__ ((section (".init9")));
313
+//int main(void) __attribute__ ((naked)) __attribute__ ((section (".init9")));
314
+void putch(char);
315
+uint8_t getch(void);
316
+static inline void getNch(uint8_t); /* "static inline" is a compiler hint to reduce code size */
317
+void verifySpace();
318
+static inline void flash_led(uint8_t);
319
+uint8_t getLen();
320
+static inline void watchdogReset();
321
+void watchdogConfig(uint8_t x);
322
+#ifdef SOFT_UART
323
+void uartDelay() __attribute__ ((naked));
324
+#endif
325
+void appStart(uint8_t rstFlags) __attribute__ ((naked));
326
+
327
+/*
328
+ * NRWW memory
329
+ * Addresses below NRWW (Non-Read-While-Write) can be programmed while
330
+ * continuing to run code from flash, slightly speeding up programming
331
+ * time. Beware that Atmel data sheets specify this as a WORD address,
332
+ * while optiboot will be comparing against a 16-bit byte address. This
333
+ * means that on a part with 128kB of memory, the upper part of the lower
334
+ * 64k will get NRWW processing as well, even though it doesn't need it.
335
+ * That's OK. In fact, you can disable the overlapping processing for
336
+ * a part entirely by setting NRWWSTART to zero. This reduces code
337
+ * space a bit, at the expense of being slightly slower, overall.
338
+ *
339
+ * RAMSTART should be self-explanatory. It's bigger on parts with a
340
+ * lot of peripheral registers.
341
+ */
342
+#if defined(__AVR_ATmega168__)
343
+#define RAMSTART (0x100)
344
+#define NRWWSTART (0x3800)
345
+#elif defined(__AVR_ATmega328P__) || defined(__AVR_ATmega32__)
346
+#define RAMSTART (0x100)
347
+#define NRWWSTART (0x7000)
348
+#elif defined (__AVR_ATmega644P__)
349
+#define RAMSTART (0x100)
350
+#define NRWWSTART (0xE000)
351
+// correct for a bug in avr-libc
352
+#undef SIGNATURE_2
353
+#define SIGNATURE_2 0x0A
354
+#elif defined (__AVR_ATmega1284P__)
355
+#define RAMSTART (0x100)
356
+#define NRWWSTART (0xE000)
357
+#elif defined(__AVR_ATtiny84__)
358
+#define RAMSTART (0x100)
359
+#define NRWWSTART (0x0000)
360
+#elif defined(__AVR_ATmega1280__)
361
+#define RAMSTART (0x200)
362
+#define NRWWSTART (0xE000)
363
+#elif defined(__AVR_ATmega8__) || defined(__AVR_ATmega88__)
364
+#define RAMSTART (0x100)
365
+#define NRWWSTART (0x1800)
366
+#endif
367
+
368
+/* C zero initialises all global variables. However, that requires */
369
+/* These definitions are NOT zero initialised, but that doesn't matter */
370
+/* This allows us to drop the zero init code, saving us memory */
371
+#define buff ((uint8_t*)(RAMSTART))
372
+#ifdef VIRTUAL_BOOT_PARTITION
373
+#define rstVect0 (*(volatile uint16_t*)(RAMSTART + SPM_PAGESIZE + 4))
374
+#define rstVect1 (*(volatile uint16_t*)(RAMSTART + SPM_PAGESIZE + 6))
375
+#define wdtVect0 (*(volatile uint16_t*)(RAMSTART + SPM_PAGESIZE + 8))
376
+#define wdtVect1 (*(volatile uint16_t*)(RAMSTART + SPM_PAGESIZE + 10))
377
+#endif
378
+
379
+/*
380
+ * Handle devices with up to 4 uarts (eg m1280.) Rather inelegantly.
381
+ * Note that mega8/m32 still needs special handling, because ubrr is handled
382
+ * differently.
383
+ */
384
+#if UART == 0
385
+# define UART_SRA UCSR0A
386
+# define UART_SRB UCSR0B
387
+# define UART_SRC UCSR0C
388
+# define UART_SRL UBRR0L
389
+# define UART_UDR UDR0
390
+#elif UART == 1
391
+#if !defined(UDR1)
392
+#error UART == 1, but no UART1 on device
393
+#endif
394
+# define UART_SRA UCSR1A
395
+# define UART_SRB UCSR1B
396
+# define UART_SRC UCSR1C
397
+# define UART_SRL UBRR1L
398
+# define UART_UDR UDR1
399
+#elif UART == 2
400
+#if !defined(UDR2)
401
+#error UART == 2, but no UART2 on device
402
+#endif
403
+# define UART_SRA UCSR2A
404
+# define UART_SRB UCSR2B
405
+# define UART_SRC UCSR2C
406
+# define UART_SRL UBRR2L
407
+# define UART_UDR UDR2
408
+#elif UART == 3
409
+#if !defined(UDR1)
410
+#error UART == 3, but no UART3 on device
411
+#endif
412
+# define UART_SRA UCSR3A
413
+# define UART_SRB UCSR3B
414
+# define UART_SRC UCSR3C
415
+# define UART_SRL UBRR3L
416
+# define UART_UDR UDR3
417
+#endif
418
+
419
+/* main program starts here */
420
+int main(void) {
421
+ uint8_t ch;
422
+ uint32_t pmask;
423
+
424
+ /*
425
+ * Making these local and in registers prevents the need for initializing
426
+ * them, and also saves space because code no longer stores to memory.
427
+ * (initializing address keeps the compiler happy, but isn't really
428
+ * necessary, and uses 4 bytes of flash.)
429
+ */
430
+ register uint16_t address = 0;
431
+ register uint16_t length;
432
+
433
+ // After the zero init loop, this is the first code to run.
434
+ //
435
+ // This code makes the following assumptions:
436
+ // No interrupts will execute
437
+ // SP points to RAMEND
438
+ // r1 contains zero
439
+ //
440
+ // If not, uncomment the following instructions:
441
+ // cli();
442
+ asm volatile ("clr __zero_reg__");
443
+ SP=RAMEND; // This is done by hardware reset
444
+
445
+ // in case we got raw chip
446
+#if 0
447
+ pmask = (GUID3 << 24) | (GUID2 << 16) | (GUID1 << 8) | GUID0;
448
+ if(pmask == 0)
449
+ OSCCAL = 0xae;
450
+#endif
451
+
452
+ // Adaboot no-wait mod
453
+ ch = MCUSR;
454
+ MCUSR = 0;
455
+ if (ch & (_BV(WDRF) | _BV(BORF) | _BV(PORF)))
456
+ appStart(ch);
457
+
458
+ // WDT clock by 32KHz IRC
459
+ PMCR = 0x80;
460
+ PMCR = 0x93;
461
+
462
+ // system clock: 16MHz system clock
463
+ CLKPR = 0x80;
464
+ CLKPR = 0x01;
465
+
466
+ // enable 1KB E2PROM (for LGT8F328P)
467
+ ECCR = 0x80;
468
+ ECCR = 0x4C;
469
+
470
+#if LED_START_FLASHES > 0
471
+ // Set up Timer 1 for timeout counter
472
+ TCCR1B = _BV(CS12) | _BV(CS10); // div 1024
473
+#endif
474
+
475
+#ifndef SOFT_UART
476
+#if defined(__AVR_ATmega8__) || defined (__AVR_ATmega32__)
477
+ UCSRA = _BV(U2X); //Double speed mode USART
478
+ UCSRB = _BV(RXEN) | _BV(TXEN); // enable Rx & Tx
479
+ UCSRC = _BV(URSEL) | _BV(UCSZ1) | _BV(UCSZ0); // config USART; 8N1
480
+ UBRRL = (uint8_t)( (F_CPU + BAUD_RATE * 4L) / (BAUD_RATE * 8L) - 1 );
481
+#else
482
+ //UART_SRA = _BV(U2X0); //Double speed mode USART0
483
+ UART_SRB = _BV(RXEN0) | _BV(TXEN0);
484
+ UART_SRC = _BV(UCSZ00) | _BV(UCSZ01);
485
+ //UART_SRL = (uint8_t)( F_CPU / (BAUD_RATE * 8L) - 1 );
486
+ UART_SRL = (uint8_t)( F_CPU / (BAUD_RATE * 16L) - 1 );
487
+#endif
488
+#endif
489
+
490
+ // Set up watchdog to trigger after 500ms
491
+ watchdogConfig(WATCHDOG_32MS);
492
+
493
+#if (LED_START_FLASHES > 0) || defined(LED_DATA_FLASH)
494
+ /* Set LED pin as output */
495
+ LED_DDR |= _BV(LED);
496
+#endif
497
+
498
+#ifdef SOFT_UART
499
+ /* Set TX pin as output */
500
+ UART_DDR |= _BV(UART_TX_BIT);
501
+#endif
502
+
503
+#if LED_START_FLASHES > 0
504
+ /* Flash onboard LED to signal entering of bootloader */
505
+ flash_led(LED_START_FLASHES * 2);
506
+#endif
507
+
508
+ // page erased flag
509
+ pmask = 0;
510
+
511
+ /* Forever loop */
512
+ for (;;) {
513
+ /* get character from UART */
514
+ ch = getch();
515
+
516
+ if(ch == STK_GET_PARAMETER) {
517
+ unsigned char which = getch();
518
+ verifySpace();
519
+ if (which == 0x82) {
520
+ /*
521
+ * Send optiboot version as "minor SW version"
522
+ */
523
+ putch(OPTIBOOT_MINVER);
524
+ } else if (which == 0x81) {
525
+ putch(OPTIBOOT_MAJVER);
526
+ } else {
527
+ /*
528
+ * GET PARAMETER returns a generic 0x03 reply for
529
+ * other parameters - enough to keep Avrdude happy
530
+ */
531
+ putch(0x03);
532
+ }
533
+ }
534
+ else if(ch == STK_SET_DEVICE) {
535
+ // SET DEVICE is ignored
536
+ getNch(20);
537
+ }
538
+ else if(ch == STK_SET_DEVICE_EXT) {
539
+ // SET DEVICE EXT is ignored
540
+ getNch(5);
541
+ }
542
+ else if(ch == STK_LOAD_ADDRESS) {
543
+ // LOAD ADDRESS
544
+ uint16_t newAddress;
545
+ newAddress = getch();
546
+ newAddress = (newAddress & 0xff) | (getch() << 8);
547
+#ifdef RAMPZ
548
+ // Transfer top bit to RAMPZ
549
+ RAMPZ = (newAddress & 0x8000) ? 1 : 0;
550
+#endif
551
+ newAddress += newAddress; // Convert from word address to byte address
552
+ address = newAddress;
553
+ verifySpace();
554
+ }
555
+ else if(ch == STK_UNIVERSAL) {
556
+ // UNIVERSAL command is ignored
557
+ getNch(4);
558
+ putch(0x00);
559
+ }
560
+ /* Write memory, length is big endian and is in bytes */
561
+ else if(ch == STK_PROG_PAGE) {
562
+ // PROGRAM PAGE - we support flash programming only, not EEPROM
563
+ uint8_t *bufPtr;
564
+ uint8_t bval;
565
+ uint16_t len;
566
+ length = (uint16_t)getch() << 8; /* getlen() */
567
+ length += getch();
568
+ bval = getch();
569
+
570
+ // If we are in RWW section, immediately start page erase
571
+ //if (address < NRWWSTART) __boot_page_erase_short((uint16_t)(void*)address);
572
+
573
+ // While that is going on, read in page contents
574
+ bufPtr = buff;
575
+ len = length;
576
+ do *bufPtr++ = getch();
577
+ while (--len);
578
+
579
+ EEARL = 0;
580
+ EEARH = address >> 8;
581
+ ch = EEARH >> 2; // 1KB page size
582
+
583
+ if((0 == (pmask & (((uint32_t)1 << ch)))) && bval == 'F') {
584
+ pmask |= ((uint32_t)1 << ch);
585
+ // do page erase here
586
+ EECR = 0x94;
587
+ EECR = 0x92;
588
+ __asm__ __volatile__ ("nop" ::);
589
+ __asm__ __volatile__ ("nop" ::);
590
+ }
591
+
592
+ // Read command terminator, start reply
593
+ verifySpace();
594
+
595
+ // If only a partial page is to be programmed, the erase might not be complete.
596
+ // So check that here
597
+ //boot_spm_busy_wait();
598
+ if (bval == 'E') {
599
+ for(len = 0; len < length; len++) {
600
+ //if(address >= 1022)
601
+ //break;
602
+ EEARL = address++;
603
+ EEARH = address >> 8;
604
+ EEDR = buff[len];
605
+ EECR = 0x04;
606
+ EECR = 0x02;
607
+ }
608
+ } else {
609
+#ifdef VIRTUAL_BOOT_PARTITION
610
+ if ((uint16_t)(void*)address == 0) {
611
+ // This is the reset vector page. We need to live-patch the code so the
612
+ // bootloader runs.
613
+ //
614
+ // Move RESET vector to WDT vector
615
+ rstVect0 = buff[0] | (buff[1] << 8);
616
+ rstVect1 = buff[2] | (buff[3] << 8);
617
+ wdtVect0 = buff[24] | (buff[25] << 8);
618
+ wdtVect1 = buff[26] | (buff[27] << 8);
619
+
620
+ buff[24] = buff[0];
621
+ buff[25] = buff[1];
622
+ buff[26] = buff[2];
623
+ buff[27] = buff[3];
624
+
625
+ // Add jump to bootloader at RESET vector
626
+ buff[0] = 0x0c;
627
+ buff[1] = 0x94; // jmp
628
+ buff[2] = 0x00;
629
+ buff[3] = 0x3a; // 0x7400 (0x3a00)
630
+ }
631
+#endif
632
+ // Write from programming buffer
633
+ pdword_t wPtr = (pdword_t)buff;
634
+ for(length = 0; length < SPM_PAGESIZE; length+=4, wPtr++) {
635
+ EEARL = 0; EEDR = wPtr->byte[0];
636
+ EEARL = 1; EEDR = wPtr->byte[1];
637
+ EEARL = 2; EEDR = wPtr->byte[2];
638
+ EEARL = 3; EEDR = wPtr->byte[3];
639
+ EEARL = (address + length) & 0xff;
640
+ EECR = 0xA4;
641
+ EECR = 0xA2;
642
+ }
643
+ }
644
+ }
645
+ /* Read memory block mode, length is big endian. */
646
+ else if(ch == STK_READ_PAGE) {
647
+ // READ PAGE - we only read flash
648
+ uint8_t bval;
649
+
650
+ length = getch() << 8; /* getlen() */
651
+ length += getch();
652
+ bval = getch();
653
+
654
+ verifySpace();
655
+
656
+ if( bval == 'E') {
657
+ do {
658
+ EEARL = address++;
659
+ EEARH = address >> 8;
660
+ EECR = 0x01;
661
+ __asm__ __volatile__ ("nop" ::);
662
+ __asm__ __volatile__ ("nop" ::);
663
+ putch(EEDR);
664
+ } while (--length);
665
+ } else {
666
+ do {
667
+#ifdef VIRTUAL_BOOT_PARTITION
668
+ // Undo vector patch in bottom page so verify passes
669
+ if (address == 0) ch = rstVect0 & 0xff;
670
+ else if (address == 1) ch = rstVect0 >> 8;
671
+ else if (address == 2) ch = rstVect1 & 0xff;
672
+ else if (address == 3) ch = rstVect1 >> 8;
673
+ else if (address == 24) ch = wdtVect0 & 0xff;
674
+ else if (address == 25) ch = wdtVect0 >> 8;
675
+ else if (address == 26) ch = wdtVect1 & 0xff;
676
+ else if (address == 27) ch = wdtVect1 >> 8;
677
+ else {
678
+ // read a Flash byte and increment the address
679
+ #if defined(RAMPZ)
680
+ // Since RAMPZ should already be set, we need to use EPLM directly.
681
+ // read a Flash and increment the address (may increment RAMPZ)
682
+ __asm__ ("elpm %0,Z\n" : "=r" (ch) : "z" (address));
683
+ #else
684
+ // read a Flash byte and increment the address
685
+ __asm__ ("lpm %0,Z\n" : "=r" (ch) : "z" (address));
686
+ //ch = *((uint8_t *)(0x4000 + address));
687
+ #endif
688
+#endif
689
+ }
690
+ address++;
691
+ putch(ch);
692
+ } while (--length);
693
+ }
694
+ }
695
+
696
+ /* Get device signature bytes */
697
+ else if(ch == STK_READ_SIGN) {
698
+ // READ SIGN - return what Avrdude wants to hear
699
+ verifySpace();
700
+ putch(SIGNATURE_0);
701
+ putch(SIGNATURE_1);
702
+ putch(SIGNATURE_2);
703
+ }
704
+ else if (ch == STK_LEAVE_PROGMODE) { /* 'Q' */
705
+ // Adaboot no-wait mod
706
+ watchdogConfig(WATCHDOG_16MS);
707
+ verifySpace();
708
+ }
709
+ else {
710
+ // This covers the response to commands like STK_ENTER_PROGMODE
711
+ verifySpace();
712
+ }
713
+ putch(STK_OK);
714
+ }
715
+}
716
+
717
+void putch(char ch) {
718
+#ifndef SOFT_UART
719
+ while (!(UART_SRA & _BV(UDRE0)));
720
+ UART_UDR = ch;
721
+#else
722
+ __asm__ __volatile__ (
723
+ " com %[ch]\n" // ones complement, carry set
724
+ " sec\n"
725
+ "1: brcc 2f\n"
726
+ " cbi %[uartPort],%[uartBit]\n"
727
+ " rjmp 3f\n"
728
+ "2: sbi %[uartPort],%[uartBit]\n"
729
+ " nop\n"
730
+ "3: rcall uartDelay\n"
731
+ " rcall uartDelay\n"
732
+ " lsr %[ch]\n"
733
+ " dec %[bitcnt]\n"
734
+ " brne 1b\n"
735
+ :
736
+ :
737
+ [bitcnt] "d" (10),
738
+ [ch] "r" (ch),
739
+ [uartPort] "I" (_SFR_IO_ADDR(UART_PORT)),
740
+ [uartBit] "I" (UART_TX_BIT)
741
+ :
742
+ "r25"
743
+ );
744
+#endif
745
+}
746
+
747
+uint8_t getch(void) {
748
+ uint8_t ch;
749
+
750
+#ifdef LED_DATA_FLASH
751
+ LED_PORT ^= _BV(LED);
752
+#endif
753
+
754
+#ifdef SOFT_UART
755
+ __asm__ __volatile__ (
756
+ "1: sbic %[uartPin],%[uartBit]\n" // Wait for start edge
757
+ " rjmp 1b\n"
758
+ " rcall uartDelay\n" // Get to middle of start bit
759
+ "2: rcall uartDelay\n" // Wait 1 bit period
760
+ " rcall uartDelay\n" // Wait 1 bit period
761
+ " clc\n"
762
+ " sbic %[uartPin],%[uartBit]\n"
763
+ " sec\n"
764
+ " dec %[bitCnt]\n"
765
+ " breq 3f\n"
766
+ " ror %[ch]\n"
767
+ " rjmp 2b\n"
768
+ "3:\n"
769
+ :
770
+ [ch] "=r" (ch)
771
+ :
772
+ [bitCnt] "d" (9),
773
+ [uartPin] "I" (_SFR_IO_ADDR(UART_PIN)),
774
+ [uartBit] "I" (UART_RX_BIT)
775
+ :
776
+ "r25"
777
+);
778
+#else
779
+ while(!(UART_SRA & _BV(RXC0)))
780
+ ;
781
+ if (!(UART_SRA & _BV(FE0))) {
782
+ /*
783
+ * A Framing Error indicates (probably) that something is talking
784
+ * to us at the wrong bit rate. Assume that this is because it
785
+ * expects to be talking to the application, and DON'T reset the
786
+ * watchdog. This should cause the bootloader to abort and run
787
+ * the application "soon", if it keeps happening. (Note that we
788
+ * don't care that an invalid char is returned...)
789
+ */
790
+ watchdogReset();
791
+ }
792
+
793
+ ch = UART_UDR;
794
+#endif
795
+
796
+#ifdef LED_DATA_FLASH
797
+ LED_PORT ^= _BV(LED);
798
+#endif
799
+
800
+ return ch;
801
+}
802
+
803
+// AVR305 equation: #define UART_B_VALUE (((F_CPU/BAUD_RATE)-23)/6)
804
+// Adding 3 to numerator simulates nearest rounding for more accurate baud rates
805
+#define UART_B_VALUE (((F_CPU/BAUD_RATE)-20)/6)
806
+#if UART_B_VALUE > 255
807
+#error Baud rate too slow for soft UART
808
+#endif
809
+
810
+void uartDelay() {
811
+ __asm__ __volatile__ (
812
+ "ldi r25,%[count]\n"
813
+ "1:dec r25\n"
814
+ "brne 1b\n"
815
+ "ret\n"
816
+ ::[count] "M" (UART_B_VALUE)
817
+ );
818
+}
819
+
820
+void getNch(uint8_t count) {
821
+ do getch(); while (--count);
822
+ verifySpace();
823
+}
824
+
825
+void verifySpace() {
826
+ if (getch() != CRC_EOP) {
827
+ watchdogConfig(WATCHDOG_32MS); // shorten WD timeout
828
+ while (1) // and busy-loop so that WD causes
829
+ ; // a reset and app start.
830
+ }
831
+ putch(STK_INSYNC);
832
+}
833
+
834
+#if LED_START_FLASHES > 0
835
+void flash_led(uint8_t count) {
836
+ do {
837
+ TCNT1 = -(F_CPU/(1024*16));
838
+ TIFR1 = _BV(TOV1);
839
+ while(!(TIFR1 & _BV(TOV1)));
840
+ LED_PORT ^= _BV(LED);
841
+ watchdogReset();
842
+ } while (--count);
843
+}
844
+#endif
845
+
846
+// Watchdog functions. These are only safe with interrupts turned off.
847
+void watchdogReset() {
848
+ __asm__ __volatile__ (
849
+ "wdr\n"
850
+ );
851
+}
852
+
853
+void watchdogConfig(uint8_t x) {
854
+#if 1
855
+ WDTCSR = _BV(WDCE) | _BV(WDE);
856
+ WDTCSR = x;
857
+#endif
858
+}
859
+
860
+void appStart(uint8_t rstFlags) {
861
+ // save the reset flags in the designated register
862
+ // This can be saved in a main program by putting code in .init0 (which
863
+ // executes before normal c init code) to save R2 to a global variable.
864
+ __asm__ __volatile__ ("mov r2, %0\n" :: "r" (rstFlags));
865
+
866
+ watchdogConfig(WATCHDOG_OFF);
867
+ __asm__ __volatile__ (
868
+#ifdef VIRTUAL_BOOT_PARTITION
869
+ // Jump to WDT vector
870
+ "ldi r30,0x0c\n"
871
+ "clr r31\n"
872
+#else
873
+ // Jump to RST vector
874
+ "clr r30\n"
875
+ "clr r31\n"
876
+#endif
877
+ "ijmp\n"
878
+ );
879
+}
Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/optiboot_lgt8fx8p/optiboot_lgt8f328p.elf
... ...
Binary files /dev/null and b/Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/optiboot_lgt8fx8p/optiboot_lgt8f328p.elf differ
Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/optiboot_lgt8fx8p/optiboot_lgt8f328p.hex
... ...
@@ -0,0 +1,67 @@
1
+:040000000C94003A22
2
+:1074000011248FEF98E09EBF8DBF94B714BE892FD3
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+:107410008D7011F0892FE0D190E89093F20083E90C
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+:10775000B7CFCE0CDF1C0EC0853739F42DD08EE1AB
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+:107760000CD085E90AD08FE09FCE813511F48CE0F2
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+:107770001DD022D080E101D08ACE982F8091C00008
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+:1077800085FFFCCF9093C60008958091C00087FFCD
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+:10779000FCCF8091C00084FD01C0A8958091C600F7
60
+:1077A00008959AE29A95F1F708950895E0E6F0E0D9
61
+:1077B00098E1908380830895E8DF803219F08DE0AE
62
+:1077C000F5DFFFCF84E1D9CF1F93182FDEDF1150F3
63
+:1077D000E9F7F2DF1F910895282E80E0E7DFECE063
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+:0477E000FF270994E2
65
+:0277FE00000584
66
+:040000030000740085
67
+:00000001FF
Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/optiboot_lgt8fx8p/optiboot_lgt8f328p.lst
... ...
@@ -0,0 +1,892 @@
1
+
2
+optiboot_lgt8f328p.elf: file format elf32-avr
3
+
4
+Sections:
5
+Idx Name Size VMA LMA File off Algn
6
+ 0 .text 000003e4 00007400 00007400 00000054 2**1
7
+ CONTENTS, ALLOC, LOAD, READONLY, CODE
8
+ 1 .bootv 00000004 00000000 00000000 00000438 2**0
9
+ CONTENTS, READONLY
10
+ 2 .version 00000002 000077fe 000077fe 0000043c 2**0
11
+ CONTENTS, READONLY
12
+ 3 .debug_aranges 00000028 00000000 00000000 0000043e 2**0
13
+ CONTENTS, READONLY, DEBUGGING
14
+ 4 .debug_pubnames 0000006d 00000000 00000000 00000466 2**0
15
+ CONTENTS, READONLY, DEBUGGING
16
+ 5 .debug_info 00000337 00000000 00000000 000004d3 2**0
17
+ CONTENTS, READONLY, DEBUGGING
18
+ 6 .debug_abbrev 000001a6 00000000 00000000 0000080a 2**0
19
+ CONTENTS, READONLY, DEBUGGING
20
+ 7 .debug_line 0000059e 00000000 00000000 000009b0 2**0
21
+ CONTENTS, READONLY, DEBUGGING
22
+ 8 .debug_frame 00000090 00000000 00000000 00000f50 2**2
23
+ CONTENTS, READONLY, DEBUGGING
24
+ 9 .debug_str 0000016b 00000000 00000000 00000fe0 2**0
25
+ CONTENTS, READONLY, DEBUGGING
26
+ 10 .debug_loc 00000344 00000000 00000000 0000114b 2**0
27
+ CONTENTS, READONLY, DEBUGGING
28
+ 11 .debug_ranges 00000080 00000000 00000000 0000148f 2**0
29
+ CONTENTS, READONLY, DEBUGGING
30
+
31
+Disassembly of section .text:
32
+
33
+00007400 <main>:
34
+# define UART_SRL UBRR3L
35
+# define UART_UDR UDR3
36
+#endif
37
+
38
+/* main program starts here */
39
+int main(void) {
40
+ 7400: 11 24 eor r1, r1
41
+ // r1 contains zero
42
+ //
43
+ // If not, uncomment the following instructions:
44
+ // cli();
45
+ asm volatile ("clr __zero_reg__");
46
+ SP=RAMEND; // This is done by hardware reset
47
+ 7402: 8f ef ldi r24, 0xFF ; 255
48
+ 7404: 98 e0 ldi r25, 0x08 ; 8
49
+ 7406: 9e bf out 0x3e, r25 ; 62
50
+ 7408: 8d bf out 0x3d, r24 ; 61
51
+ if(pmask == 0)
52
+ OSCCAL = 0xae;
53
+#endif
54
+
55
+ // Adaboot no-wait mod
56
+ ch = MCUSR;
57
+ 740a: 94 b7 in r25, 0x34 ; 52
58
+ MCUSR = 0;
59
+ 740c: 14 be out 0x34, r1 ; 52
60
+ if (ch & (_BV(WDRF) | _BV(BORF) | _BV(PORF)))
61
+ 740e: 89 2f mov r24, r25
62
+ 7410: 8d 70 andi r24, 0x0D ; 13
63
+ 7412: 11 f0 breq .+4 ; 0x7418 <main+0x18>
64
+ appStart(ch);
65
+ 7414: 89 2f mov r24, r25
66
+ 7416: e0 d1 rcall .+960 ; 0x77d8 <appStart>
67
+
68
+ // WDT clock by 32KHz IRC
69
+ PMCR = 0x80;
70
+ 7418: 90 e8 ldi r25, 0x80 ; 128
71
+ 741a: 90 93 f2 00 sts 0x00F2, r25
72
+ PMCR = 0x93;
73
+ 741e: 83 e9 ldi r24, 0x93 ; 147
74
+ 7420: 80 93 f2 00 sts 0x00F2, r24
75
+
76
+ // system clock: 16MHz system clock
77
+ CLKPR = 0x80;
78
+ 7424: 90 93 61 00 sts 0x0061, r25
79
+ CLKPR = 0x01;
80
+ 7428: 81 e0 ldi r24, 0x01 ; 1
81
+ 742a: 80 93 61 00 sts 0x0061, r24
82
+
83
+ // enable 1KB E2PROM (for LGT8F328P)
84
+ ECCR = 0x80;
85
+ 742e: 96 bf out 0x36, r25 ; 54
86
+ ECCR = 0x4C;
87
+ 7430: 8c e4 ldi r24, 0x4C ; 76
88
+ 7432: 86 bf out 0x36, r24 ; 54
89
+
90
+#if LED_START_FLASHES > 0
91
+ // Set up Timer 1 for timeout counter
92
+ TCCR1B = _BV(CS12) | _BV(CS10); // div 1024
93
+ 7434: 85 e0 ldi r24, 0x05 ; 5
94
+ 7436: 80 93 81 00 sts 0x0081, r24
95
+ UCSRB = _BV(RXEN) | _BV(TXEN); // enable Rx & Tx
96
+ UCSRC = _BV(URSEL) | _BV(UCSZ1) | _BV(UCSZ0); // config USART; 8N1
97
+ UBRRL = (uint8_t)( (F_CPU + BAUD_RATE * 4L) / (BAUD_RATE * 8L) - 1 );
98
+#else
99
+ //UART_SRA = _BV(U2X0); //Double speed mode USART0
100
+ UART_SRB = _BV(RXEN0) | _BV(TXEN0);
101
+ 743a: 88 e1 ldi r24, 0x18 ; 24
102
+ 743c: 80 93 c1 00 sts 0x00C1, r24
103
+ UART_SRC = _BV(UCSZ00) | _BV(UCSZ01);
104
+ 7440: 86 e0 ldi r24, 0x06 ; 6
105
+ 7442: 80 93 c2 00 sts 0x00C2, r24
106
+ //UART_SRL = (uint8_t)( F_CPU / (BAUD_RATE * 8L) - 1 );
107
+ UART_SRL = (uint8_t)( F_CPU / (BAUD_RATE * 16L) - 1 );
108
+ 7446: 80 e1 ldi r24, 0x10 ; 16
109
+ 7448: 80 93 c4 00 sts 0x00C4, r24
110
+#endif
111
+#endif
112
+
113
+ // Set up watchdog to trigger after 500ms
114
+ watchdogConfig(WATCHDOG_32MS);
115
+ 744c: 8d e0 ldi r24, 0x0D ; 13
116
+ 744e: ae d1 rcall .+860 ; 0x77ac <watchdogConfig>
117
+
118
+#if (LED_START_FLASHES > 0) || defined(LED_DATA_FLASH)
119
+ /* Set LED pin as output */
120
+ LED_DDR |= _BV(LED);
121
+ 7450: 25 9a sbi 0x04, 5 ; 4
122
+ 7452: 96 e0 ldi r25, 0x06 ; 6
123
+}
124
+
125
+#if LED_START_FLASHES > 0
126
+void flash_led(uint8_t count) {
127
+ do {
128
+ TCNT1 = -(F_CPU/(1024*16));
129
+ 7454: 20 e3 ldi r18, 0x30 ; 48
130
+ 7456: 3c ef ldi r19, 0xFC ; 252
131
+ TIFR1 = _BV(TOV1);
132
+ 7458: 51 e0 ldi r21, 0x01 ; 1
133
+ while(!(TIFR1 & _BV(TOV1)));
134
+ LED_PORT ^= _BV(LED);
135
+ 745a: 40 e2 ldi r20, 0x20 ; 32
136
+}
137
+
138
+#if LED_START_FLASHES > 0
139
+void flash_led(uint8_t count) {
140
+ do {
141
+ TCNT1 = -(F_CPU/(1024*16));
142
+ 745c: 30 93 85 00 sts 0x0085, r19
143
+ 7460: 20 93 84 00 sts 0x0084, r18
144
+ TIFR1 = _BV(TOV1);
145
+ 7464: 56 bb out 0x16, r21 ; 22
146
+ while(!(TIFR1 & _BV(TOV1)));
147
+ 7466: b0 9b sbis 0x16, 0 ; 22
148
+ 7468: fe cf rjmp .-4 ; 0x7466 <main+0x66>
149
+ LED_PORT ^= _BV(LED);
150
+ 746a: 85 b1 in r24, 0x05 ; 5
151
+ 746c: 84 27 eor r24, r20
152
+ 746e: 85 b9 out 0x05, r24 ; 5
153
+}
154
+#endif
155
+
156
+// Watchdog functions. These are only safe with interrupts turned off.
157
+void watchdogReset() {
158
+ __asm__ __volatile__ (
159
+ 7470: a8 95 wdr
160
+ TCNT1 = -(F_CPU/(1024*16));
161
+ TIFR1 = _BV(TOV1);
162
+ while(!(TIFR1 & _BV(TOV1)));
163
+ LED_PORT ^= _BV(LED);
164
+ watchdogReset();
165
+ } while (--count);
166
+ 7472: 91 50 subi r25, 0x01 ; 1
167
+ 7474: 99 f7 brne .-26 ; 0x745c <main+0x5c>
168
+ 7476: 66 24 eor r6, r6
169
+ 7478: 77 24 eor r7, r7
170
+ 747a: 43 01 movw r8, r6
171
+ 747c: cc 24 eor r12, r12
172
+ 747e: dd 24 eor r13, r13
173
+ buff[26] = buff[2];
174
+ buff[27] = buff[3];
175
+
176
+ // Add jump to bootloader at RESET vector
177
+ buff[0] = 0x0c;
178
+ buff[1] = 0x94; // jmp
179
+ 7480: 64 e9 ldi r22, 0x94 ; 148
180
+ 7482: a6 2e mov r10, r22
181
+ EEARL = 0;
182
+ EEARH = address >> 8;
183
+ ch = EEARH >> 2; // 1KB page size
184
+
185
+ if((0 == (pmask & (((uint32_t)1 << ch)))) && bval == 'F') {
186
+ pmask |= ((uint32_t)1 << ch);
187
+ 7484: 51 e0 ldi r21, 0x01 ; 1
188
+ 7486: 25 2e mov r2, r21
189
+ 7488: 31 2c mov r3, r1
190
+ 748a: 41 2c mov r4, r1
191
+ 748c: 51 2c mov r5, r1
192
+ pmask = 0;
193
+
194
+ /* Forever loop */
195
+ for (;;) {
196
+ /* get character from UART */
197
+ ch = getch();
198
+ 748e: 7d d1 rcall .+762 ; 0x778a <getch>
199
+
200
+ if(ch == STK_GET_PARAMETER) {
201
+ 7490: 81 34 cpi r24, 0x41 ; 65
202
+ 7492: 61 f4 brne .+24 ; 0x74ac <main+0xac>
203
+ unsigned char which = getch();
204
+ 7494: 7a d1 rcall .+756 ; 0x778a <getch>
205
+ 7496: 18 2f mov r17, r24
206
+ verifySpace();
207
+ 7498: 8f d1 rcall .+798 ; 0x77b8 <verifySpace>
208
+ if (which == 0x82) {
209
+ 749a: 12 38 cpi r17, 0x82 ; 130
210
+ 749c: 29 f1 breq .+74 ; 0x74e8 <main+0xe8>
211
+ /*
212
+ * Send optiboot version as "minor SW version"
213
+ */
214
+ putch(OPTIBOOT_MINVER);
215
+ } else if (which == 0x81) {
216
+ 749e: 11 38 cpi r17, 0x81 ; 129
217
+ 74a0: 11 f4 brne .+4 ; 0x74a6 <main+0xa6>
218
+ putch(OPTIBOOT_MAJVER);
219
+ 74a2: 85 e0 ldi r24, 0x05 ; 5
220
+ 74a4: 01 c0 rjmp .+2 ; 0x74a8 <main+0xa8>
221
+ } else {
222
+ /*
223
+ * GET PARAMETER returns a generic 0x03 reply for
224
+ * other parameters - enough to keep Avrdude happy
225
+ */
226
+ putch(0x03);
227
+ 74a6: 83 e0 ldi r24, 0x03 ; 3
228
+ 74a8: 68 d1 rcall .+720 ; 0x777a <putch>
229
+ 74aa: 64 c1 rjmp .+712 ; 0x7774 <main+0x374>
230
+ }
231
+ }
232
+ else if(ch == STK_SET_DEVICE) {
233
+ 74ac: 82 34 cpi r24, 0x42 ; 66
234
+ 74ae: 11 f4 brne .+4 ; 0x74b4 <main+0xb4>
235
+ // SET DEVICE is ignored
236
+ getNch(20);
237
+ 74b0: 84 e1 ldi r24, 0x14 ; 20
238
+ 74b2: 03 c0 rjmp .+6 ; 0x74ba <main+0xba>
239
+ }
240
+ else if(ch == STK_SET_DEVICE_EXT) {
241
+ 74b4: 85 34 cpi r24, 0x45 ; 69
242
+ 74b6: 19 f4 brne .+6 ; 0x74be <main+0xbe>
243
+ // SET DEVICE EXT is ignored
244
+ getNch(5);
245
+ 74b8: 85 e0 ldi r24, 0x05 ; 5
246
+ 74ba: 86 d1 rcall .+780 ; 0x77c8 <verifySpace+0x10>
247
+ 74bc: 5b c1 rjmp .+694 ; 0x7774 <main+0x374>
248
+ }
249
+ else if(ch == STK_LOAD_ADDRESS) {
250
+ 74be: 85 35 cpi r24, 0x55 ; 85
251
+ 74c0: 79 f4 brne .+30 ; 0x74e0 <main+0xe0>
252
+ // LOAD ADDRESS
253
+ uint16_t newAddress;
254
+ newAddress = getch();
255
+ 74c2: 63 d1 rcall .+710 ; 0x778a <getch>
256
+ newAddress = (newAddress & 0xff) | (getch() << 8);
257
+ 74c4: e8 2e mov r14, r24
258
+ 74c6: ff 24 eor r15, r15
259
+ 74c8: 60 d1 rcall .+704 ; 0x778a <getch>
260
+ 74ca: 08 2f mov r16, r24
261
+ 74cc: 10 e0 ldi r17, 0x00 ; 0
262
+ 74ce: 10 2f mov r17, r16
263
+ 74d0: 00 27 eor r16, r16
264
+ 74d2: 0e 29 or r16, r14
265
+ 74d4: 1f 29 or r17, r15
266
+#ifdef RAMPZ
267
+ // Transfer top bit to RAMPZ
268
+ RAMPZ = (newAddress & 0x8000) ? 1 : 0;
269
+#endif
270
+ newAddress += newAddress; // Convert from word address to byte address
271
+ 74d6: 00 0f add r16, r16
272
+ 74d8: 11 1f adc r17, r17
273
+ address = newAddress;
274
+ verifySpace();
275
+ 74da: 6e d1 rcall .+732 ; 0x77b8 <verifySpace>
276
+ 74dc: 68 01 movw r12, r16
277
+ 74de: 4a c1 rjmp .+660 ; 0x7774 <main+0x374>
278
+ }
279
+ else if(ch == STK_UNIVERSAL) {
280
+ 74e0: 86 35 cpi r24, 0x56 ; 86
281
+ 74e2: 21 f4 brne .+8 ; 0x74ec <main+0xec>
282
+ // UNIVERSAL command is ignored
283
+ getNch(4);
284
+ 74e4: 84 e0 ldi r24, 0x04 ; 4
285
+ 74e6: 70 d1 rcall .+736 ; 0x77c8 <verifySpace+0x10>
286
+ putch(0x00);
287
+ 74e8: 80 e0 ldi r24, 0x00 ; 0
288
+ 74ea: de cf rjmp .-68 ; 0x74a8 <main+0xa8>
289
+ }
290
+ /* Write memory, length is big endian and is in bytes */
291
+ else if(ch == STK_PROG_PAGE) {
292
+ 74ec: 84 36 cpi r24, 0x64 ; 100
293
+ 74ee: 09 f0 breq .+2 ; 0x74f2 <main+0xf2>
294
+ 74f0: c5 c0 rjmp .+394 ; 0x767c <main+0x27c>
295
+ // PROGRAM PAGE - we support flash programming only, not EEPROM
296
+ uint8_t *bufPtr;
297
+ uint8_t bval;
298
+ uint16_t len;
299
+ length = (uint16_t)getch() << 8; /* getlen() */
300
+ 74f2: 4b d1 rcall .+662 ; 0x778a <getch>
301
+ 74f4: 90 e0 ldi r25, 0x00 ; 0
302
+ 74f6: f8 2e mov r15, r24
303
+ 74f8: ee 24 eor r14, r14
304
+ length += getch();
305
+ 74fa: 47 d1 rcall .+654 ; 0x778a <getch>
306
+ 74fc: e8 0e add r14, r24
307
+ 74fe: f1 1c adc r15, r1
308
+ bval = getch();
309
+ 7500: 44 d1 rcall .+648 ; 0x778a <getch>
310
+ 7502: b8 2e mov r11, r24
311
+ 7504: e7 01 movw r28, r14
312
+ 7506: 00 e0 ldi r16, 0x00 ; 0
313
+ 7508: 11 e0 ldi r17, 0x01 ; 1
314
+ //if (address < NRWWSTART) __boot_page_erase_short((uint16_t)(void*)address);
315
+
316
+ // While that is going on, read in page contents
317
+ bufPtr = buff;
318
+ len = length;
319
+ do *bufPtr++ = getch();
320
+ 750a: 3f d1 rcall .+638 ; 0x778a <getch>
321
+ 750c: f8 01 movw r30, r16
322
+ 750e: 81 93 st Z+, r24
323
+ 7510: 8f 01 movw r16, r30
324
+ while (--len);
325
+ 7512: 21 97 sbiw r28, 0x01 ; 1
326
+ 7514: d1 f7 brne .-12 ; 0x750a <main+0x10a>
327
+
328
+ EEARL = 0;
329
+ 7516: 11 bc out 0x21, r1 ; 33
330
+ EEARH = address >> 8;
331
+ 7518: 8d 2d mov r24, r13
332
+ 751a: 99 27 eor r25, r25
333
+ 751c: 82 bd out 0x22, r24 ; 34
334
+ ch = EEARH >> 2; // 1KB page size
335
+ 751e: 82 b5 in r24, 0x22 ; 34
336
+
337
+ if((0 == (pmask & (((uint32_t)1 << ch)))) && bval == 'F') {
338
+ 7520: 86 95 lsr r24
339
+ 7522: 86 95 lsr r24
340
+ 7524: 28 2f mov r18, r24
341
+ 7526: d4 01 movw r26, r8
342
+ 7528: c3 01 movw r24, r6
343
+ 752a: 02 2e mov r0, r18
344
+ 752c: 04 c0 rjmp .+8 ; 0x7536 <main+0x136>
345
+ 752e: b6 95 lsr r27
346
+ 7530: a7 95 ror r26
347
+ 7532: 97 95 ror r25
348
+ 7534: 87 95 ror r24
349
+ 7536: 0a 94 dec r0
350
+ 7538: d2 f7 brpl .-12 ; 0x752e <main+0x12e>
351
+ 753a: 80 fd sbrc r24, 0
352
+ 753c: 15 c0 rjmp .+42 ; 0x7568 <main+0x168>
353
+ 753e: f6 e4 ldi r31, 0x46 ; 70
354
+ 7540: bf 16 cp r11, r31
355
+ 7542: 91 f4 brne .+36 ; 0x7568 <main+0x168>
356
+ pmask |= ((uint32_t)1 << ch);
357
+ 7544: d2 01 movw r26, r4
358
+ 7546: c1 01 movw r24, r2
359
+ 7548: 04 c0 rjmp .+8 ; 0x7552 <main+0x152>
360
+ 754a: 88 0f add r24, r24
361
+ 754c: 99 1f adc r25, r25
362
+ 754e: aa 1f adc r26, r26
363
+ 7550: bb 1f adc r27, r27
364
+ 7552: 2a 95 dec r18
365
+ 7554: d2 f7 brpl .-12 ; 0x754a <main+0x14a>
366
+ 7556: 68 2a or r6, r24
367
+ 7558: 79 2a or r7, r25
368
+ 755a: 8a 2a or r8, r26
369
+ 755c: 9b 2a or r9, r27
370
+ // do page erase here
371
+ EECR = 0x94;
372
+ 755e: af ba out 0x1f, r10 ; 31
373
+ EECR = 0x92;
374
+ 7560: 82 e9 ldi r24, 0x92 ; 146
375
+ 7562: 8f bb out 0x1f, r24 ; 31
376
+ __asm__ __volatile__ ("nop" ::);
377
+ 7564: 00 00 nop
378
+ __asm__ __volatile__ ("nop" ::);
379
+ 7566: 00 00 nop
380
+ }
381
+
382
+ // Read command terminator, start reply
383
+ verifySpace();
384
+ 7568: 27 d1 rcall .+590 ; 0x77b8 <verifySpace>
385
+
386
+ // If only a partial page is to be programmed, the erase might not be complete.
387
+ // So check that here
388
+ //boot_spm_busy_wait();
389
+ if (bval == 'E') {
390
+ 756a: e5 e4 ldi r30, 0x45 ; 69
391
+ 756c: be 16 cp r11, r30
392
+ 756e: b1 f4 brne .+44 ; 0x759c <main+0x19c>
393
+ 7570: 96 01 movw r18, r12
394
+ 7572: 10 c0 rjmp .+32 ; 0x7594 <main+0x194>
395
+ for(len = 0; len < length; len++) {
396
+ //if(address >= 1022)
397
+ //break;
398
+ EEARL = address++;
399
+ 7574: 21 bd out 0x21, r18 ; 33
400
+ 7576: 2f 5f subi r18, 0xFF ; 255
401
+ 7578: 3f 4f sbci r19, 0xFF ; 255
402
+ EEARH = address >> 8;
403
+ 757a: 83 2f mov r24, r19
404
+ 757c: 99 27 eor r25, r25
405
+ 757e: 82 bd out 0x22, r24 ; 34
406
+ EEDR = buff[len];
407
+ 7580: c0 50 subi r28, 0x00 ; 0
408
+ 7582: df 4f sbci r29, 0xFF ; 255
409
+ 7584: 88 81 ld r24, Y
410
+ 7586: 80 bd out 0x20, r24 ; 32
411
+ EECR = 0x04;
412
+ 7588: f4 e0 ldi r31, 0x04 ; 4
413
+ 758a: ff bb out 0x1f, r31 ; 31
414
+ EECR = 0x02;
415
+ 758c: 82 e0 ldi r24, 0x02 ; 2
416
+ 758e: 8f bb out 0x1f, r24 ; 31
417
+
418
+ // If only a partial page is to be programmed, the erase might not be complete.
419
+ // So check that here
420
+ //boot_spm_busy_wait();
421
+ if (bval == 'E') {
422
+ for(len = 0; len < length; len++) {
423
+ 7590: cf 5f subi r28, 0xFF ; 255
424
+ 7592: d0 40 sbci r29, 0x00 ; 0
425
+ 7594: ce 15 cp r28, r14
426
+ 7596: df 05 cpc r29, r15
427
+ 7598: 68 f3 brcs .-38 ; 0x7574 <main+0x174>
428
+ 759a: db c0 rjmp .+438 ; 0x7752 <main+0x352>
429
+ EECR = 0x04;
430
+ EECR = 0x02;
431
+ }
432
+ } else {
433
+#ifdef VIRTUAL_BOOT_PARTITION
434
+ if ((uint16_t)(void*)address == 0) {
435
+ 759c: c1 14 cp r12, r1
436
+ 759e: d1 04 cpc r13, r1
437
+ 75a0: 09 f0 breq .+2 ; 0x75a4 <main+0x1a4>
438
+ 75a2: 4e c0 rjmp .+156 ; 0x7640 <main+0x240>
439
+ // This is the reset vector page. We need to live-patch the code so the
440
+ // bootloader runs.
441
+ //
442
+ // Move RESET vector to WDT vector
443
+ rstVect0 = buff[0] | (buff[1] << 8);
444
+ 75a4: 60 91 00 01 lds r22, 0x0100
445
+ 75a8: 70 91 01 01 lds r23, 0x0101
446
+ 75ac: 87 2f mov r24, r23
447
+ 75ae: 90 e0 ldi r25, 0x00 ; 0
448
+ 75b0: 98 2f mov r25, r24
449
+ 75b2: 88 27 eor r24, r24
450
+ 75b4: 26 2f mov r18, r22
451
+ 75b6: 30 e0 ldi r19, 0x00 ; 0
452
+ 75b8: 82 2b or r24, r18
453
+ 75ba: 93 2b or r25, r19
454
+ 75bc: 90 93 85 01 sts 0x0185, r25
455
+ 75c0: 80 93 84 01 sts 0x0184, r24
456
+ rstVect1 = buff[2] | (buff[3] << 8);
457
+ 75c4: 40 91 02 01 lds r20, 0x0102
458
+ 75c8: 50 91 03 01 lds r21, 0x0103
459
+ 75cc: 85 2f mov r24, r21
460
+ 75ce: 90 e0 ldi r25, 0x00 ; 0
461
+ 75d0: 98 2f mov r25, r24
462
+ 75d2: 88 27 eor r24, r24
463
+ 75d4: 24 2f mov r18, r20
464
+ 75d6: 30 e0 ldi r19, 0x00 ; 0
465
+ 75d8: 82 2b or r24, r18
466
+ 75da: 93 2b or r25, r19
467
+ 75dc: 90 93 87 01 sts 0x0187, r25
468
+ 75e0: 80 93 86 01 sts 0x0186, r24
469
+ wdtVect0 = buff[24] | (buff[25] << 8);
470
+ 75e4: 20 91 18 01 lds r18, 0x0118
471
+ 75e8: 80 91 19 01 lds r24, 0x0119
472
+ 75ec: 90 e0 ldi r25, 0x00 ; 0
473
+ 75ee: 98 2f mov r25, r24
474
+ 75f0: 88 27 eor r24, r24
475
+ 75f2: 30 e0 ldi r19, 0x00 ; 0
476
+ 75f4: 82 2b or r24, r18
477
+ 75f6: 93 2b or r25, r19
478
+ 75f8: 90 93 89 01 sts 0x0189, r25
479
+ 75fc: 80 93 88 01 sts 0x0188, r24
480
+ wdtVect1 = buff[26] | (buff[27] << 8);
481
+ 7600: 20 91 1a 01 lds r18, 0x011A
482
+ 7604: 80 91 1b 01 lds r24, 0x011B
483
+ 7608: 90 e0 ldi r25, 0x00 ; 0
484
+ 760a: 98 2f mov r25, r24
485
+ 760c: 88 27 eor r24, r24
486
+ 760e: 30 e0 ldi r19, 0x00 ; 0
487
+ 7610: 82 2b or r24, r18
488
+ 7612: 93 2b or r25, r19
489
+ 7614: 90 93 8b 01 sts 0x018B, r25
490
+ 7618: 80 93 8a 01 sts 0x018A, r24
491
+
492
+ buff[24] = buff[0];
493
+ 761c: 60 93 18 01 sts 0x0118, r22
494
+ buff[25] = buff[1];
495
+ 7620: 70 93 19 01 sts 0x0119, r23
496
+ buff[26] = buff[2];
497
+ 7624: 40 93 1a 01 sts 0x011A, r20
498
+ buff[27] = buff[3];
499
+ 7628: 50 93 1b 01 sts 0x011B, r21
500
+
501
+ // Add jump to bootloader at RESET vector
502
+ buff[0] = 0x0c;
503
+ 762c: 8c e0 ldi r24, 0x0C ; 12
504
+ 762e: 80 93 00 01 sts 0x0100, r24
505
+ buff[1] = 0x94; // jmp
506
+ 7632: a0 92 01 01 sts 0x0101, r10
507
+ buff[2] = 0x00;
508
+ 7636: 10 92 02 01 sts 0x0102, r1
509
+ buff[3] = 0x3a; // 0x7400 (0x3a00)
510
+ 763a: ea e3 ldi r30, 0x3A ; 58
511
+ 763c: e0 93 03 01 sts 0x0103, r30
512
+ 7640: e0 e0 ldi r30, 0x00 ; 0
513
+ 7642: f1 e0 ldi r31, 0x01 ; 1
514
+ }
515
+#endif
516
+ // Write from programming buffer
517
+ pdword_t wPtr = (pdword_t)buff;
518
+ for(length = 0; length < SPM_PAGESIZE; length+=4, wPtr++) {
519
+ EEARL = 0; EEDR = wPtr->byte[0];
520
+ 7644: 11 bc out 0x21, r1 ; 33
521
+ 7646: 80 81 ld r24, Z
522
+ 7648: 80 bd out 0x20, r24 ; 32
523
+ EEARL = 1; EEDR = wPtr->byte[1];
524
+ 764a: 81 e0 ldi r24, 0x01 ; 1
525
+ 764c: 81 bd out 0x21, r24 ; 33
526
+ 764e: 81 81 ldd r24, Z+1 ; 0x01
527
+ 7650: 80 bd out 0x20, r24 ; 32
528
+ EEARL = 2; EEDR = wPtr->byte[2];
529
+ 7652: 82 e0 ldi r24, 0x02 ; 2
530
+ 7654: 81 bd out 0x21, r24 ; 33
531
+ 7656: 82 81 ldd r24, Z+2 ; 0x02
532
+ 7658: 80 bd out 0x20, r24 ; 32
533
+ EEARL = 3; EEDR = wPtr->byte[3];
534
+ 765a: 83 e0 ldi r24, 0x03 ; 3
535
+ 765c: 81 bd out 0x21, r24 ; 33
536
+ 765e: 83 81 ldd r24, Z+3 ; 0x03
537
+ 7660: 80 bd out 0x20, r24 ; 32
538
+ 7662: 8e 2f mov r24, r30
539
+ 7664: 8c 0d add r24, r12
540
+ EEARL = (address + length) & 0xff;
541
+ 7666: 81 bd out 0x21, r24 ; 33
542
+ EECR = 0xA4;
543
+ 7668: 84 ea ldi r24, 0xA4 ; 164
544
+ 766a: 8f bb out 0x1f, r24 ; 31
545
+ EECR = 0xA2;
546
+ 766c: 82 ea ldi r24, 0xA2 ; 162
547
+ 766e: 8f bb out 0x1f, r24 ; 31
548
+ buff[3] = 0x3a; // 0x7400 (0x3a00)
549
+ }
550
+#endif
551
+ // Write from programming buffer
552
+ pdword_t wPtr = (pdword_t)buff;
553
+ for(length = 0; length < SPM_PAGESIZE; length+=4, wPtr++) {
554
+ 7670: 34 96 adiw r30, 0x04 ; 4
555
+ 7672: 81 e0 ldi r24, 0x01 ; 1
556
+ 7674: e0 38 cpi r30, 0x80 ; 128
557
+ 7676: f8 07 cpc r31, r24
558
+ 7678: 29 f7 brne .-54 ; 0x7644 <main+0x244>
559
+ 767a: 7c c0 rjmp .+248 ; 0x7774 <main+0x374>
560
+ EECR = 0xA2;
561
+ }
562
+ }
563
+ }
564
+ /* Read memory block mode, length is big endian. */
565
+ else if(ch == STK_READ_PAGE) {
566
+ 767c: 84 37 cpi r24, 0x74 ; 116
567
+ 767e: 09 f0 breq .+2 ; 0x7682 <main+0x282>
568
+ 7680: 6b c0 rjmp .+214 ; 0x7758 <main+0x358>
569
+ // READ PAGE - we only read flash
570
+ uint8_t bval;
571
+
572
+ length = getch() << 8; /* getlen() */
573
+ 7682: 83 d0 rcall .+262 ; 0x778a <getch>
574
+ 7684: 90 e0 ldi r25, 0x00 ; 0
575
+ 7686: f8 2e mov r15, r24
576
+ 7688: ee 24 eor r14, r14
577
+ length += getch();
578
+ 768a: 7f d0 rcall .+254 ; 0x778a <getch>
579
+ 768c: e8 0e add r14, r24
580
+ 768e: f1 1c adc r15, r1
581
+ bval = getch();
582
+ 7690: 7c d0 rcall .+248 ; 0x778a <getch>
583
+ 7692: 18 2f mov r17, r24
584
+
585
+ verifySpace();
586
+ 7694: 91 d0 rcall .+290 ; 0x77b8 <verifySpace>
587
+
588
+ if( bval == 'E') {
589
+ 7696: 15 34 cpi r17, 0x45 ; 69
590
+ 7698: 89 f4 brne .+34 ; 0x76bc <main+0x2bc>
591
+ 769a: e6 01 movw r28, r12
592
+ 769c: 87 01 movw r16, r14
593
+ do {
594
+ EEARL = address++;
595
+ 769e: c1 bd out 0x21, r28 ; 33
596
+ 76a0: 21 96 adiw r28, 0x01 ; 1
597
+ EEARH = address >> 8;
598
+ 76a2: 8d 2f mov r24, r29
599
+ 76a4: 99 27 eor r25, r25
600
+ 76a6: 82 bd out 0x22, r24 ; 34
601
+ EECR = 0x01;
602
+ 76a8: e1 e0 ldi r30, 0x01 ; 1
603
+ 76aa: ef bb out 0x1f, r30 ; 31
604
+ __asm__ __volatile__ ("nop" ::);
605
+ 76ac: 00 00 nop
606
+ __asm__ __volatile__ ("nop" ::);
607
+ 76ae: 00 00 nop
608
+ putch(EEDR);
609
+ 76b0: 80 b5 in r24, 0x20 ; 32
610
+ 76b2: 63 d0 rcall .+198 ; 0x777a <putch>
611
+ } while (--length);
612
+ 76b4: 01 50 subi r16, 0x01 ; 1
613
+ 76b6: 10 40 sbci r17, 0x00 ; 0
614
+ 76b8: 91 f7 brne .-28 ; 0x769e <main+0x29e>
615
+ 76ba: 4b c0 rjmp .+150 ; 0x7752 <main+0x352>
616
+ 76bc: e6 01 movw r28, r12
617
+ 76be: 87 01 movw r16, r14
618
+ } else {
619
+ do {
620
+#ifdef VIRTUAL_BOOT_PARTITION
621
+ // Undo vector patch in bottom page so verify passes
622
+ if (address == 0) ch = rstVect0 & 0xff;
623
+ 76c0: 20 97 sbiw r28, 0x00 ; 0
624
+ 76c2: 29 f4 brne .+10 ; 0x76ce <main+0x2ce>
625
+ 76c4: 80 91 84 01 lds r24, 0x0184
626
+ 76c8: 90 91 85 01 lds r25, 0x0185
627
+ 76cc: 3c c0 rjmp .+120 ; 0x7746 <main+0x346>
628
+ else if (address == 1) ch = rstVect0 >> 8;
629
+ 76ce: c1 30 cpi r28, 0x01 ; 1
630
+ 76d0: d1 05 cpc r29, r1
631
+ 76d2: 29 f4 brne .+10 ; 0x76de <main+0x2de>
632
+ 76d4: 80 91 84 01 lds r24, 0x0184
633
+ 76d8: 90 91 85 01 lds r25, 0x0185
634
+ 76dc: 0f c0 rjmp .+30 ; 0x76fc <main+0x2fc>
635
+ else if (address == 2) ch = rstVect1 & 0xff;
636
+ 76de: c2 30 cpi r28, 0x02 ; 2
637
+ 76e0: d1 05 cpc r29, r1
638
+ 76e2: 29 f4 brne .+10 ; 0x76ee <main+0x2ee>
639
+ 76e4: 80 91 86 01 lds r24, 0x0186
640
+ 76e8: 90 91 87 01 lds r25, 0x0187
641
+ 76ec: 2c c0 rjmp .+88 ; 0x7746 <main+0x346>
642
+ else if (address == 3) ch = rstVect1 >> 8;
643
+ 76ee: c3 30 cpi r28, 0x03 ; 3
644
+ 76f0: d1 05 cpc r29, r1
645
+ 76f2: 39 f4 brne .+14 ; 0x7702 <main+0x302>
646
+ 76f4: 80 91 86 01 lds r24, 0x0186
647
+ 76f8: 90 91 87 01 lds r25, 0x0187
648
+ 76fc: 89 2f mov r24, r25
649
+ 76fe: 99 27 eor r25, r25
650
+ 7700: 22 c0 rjmp .+68 ; 0x7746 <main+0x346>
651
+ else if (address == 24) ch = wdtVect0 & 0xff;
652
+ 7702: c8 31 cpi r28, 0x18 ; 24
653
+ 7704: d1 05 cpc r29, r1
654
+ 7706: 29 f4 brne .+10 ; 0x7712 <main+0x312>
655
+ 7708: 80 91 88 01 lds r24, 0x0188
656
+ 770c: 90 91 89 01 lds r25, 0x0189
657
+ 7710: 1a c0 rjmp .+52 ; 0x7746 <main+0x346>
658
+ else if (address == 25) ch = wdtVect0 >> 8;
659
+ 7712: c9 31 cpi r28, 0x19 ; 25
660
+ 7714: d1 05 cpc r29, r1
661
+ 7716: 29 f4 brne .+10 ; 0x7722 <main+0x322>
662
+ 7718: 80 91 88 01 lds r24, 0x0188
663
+ 771c: 90 91 89 01 lds r25, 0x0189
664
+ 7720: ed cf rjmp .-38 ; 0x76fc <main+0x2fc>
665
+ else if (address == 26) ch = wdtVect1 & 0xff;
666
+ 7722: ca 31 cpi r28, 0x1A ; 26
667
+ 7724: d1 05 cpc r29, r1
668
+ 7726: 29 f4 brne .+10 ; 0x7732 <main+0x332>
669
+ 7728: 80 91 8a 01 lds r24, 0x018A
670
+ 772c: 90 91 8b 01 lds r25, 0x018B
671
+ 7730: 0a c0 rjmp .+20 ; 0x7746 <main+0x346>
672
+ else if (address == 27) ch = wdtVect1 >> 8;
673
+ 7732: cb 31 cpi r28, 0x1B ; 27
674
+ 7734: d1 05 cpc r29, r1
675
+ 7736: 29 f4 brne .+10 ; 0x7742 <main+0x342>
676
+ 7738: 80 91 8a 01 lds r24, 0x018A
677
+ 773c: 90 91 8b 01 lds r25, 0x018B
678
+ 7740: dd cf rjmp .-70 ; 0x76fc <main+0x2fc>
679
+ // Since RAMPZ should already be set, we need to use EPLM directly.
680
+ // read a Flash and increment the address (may increment RAMPZ)
681
+ __asm__ ("elpm %0,Z\n" : "=r" (ch) : "z" (address));
682
+ #else
683
+ // read a Flash byte and increment the address
684
+ __asm__ ("lpm %0,Z\n" : "=r" (ch) : "z" (address));
685
+ 7742: fe 01 movw r30, r28
686
+ 7744: 84 91 lpm r24, Z+
687
+ //ch = *((uint8_t *)(0x4000 + address));
688
+ #endif
689
+#endif
690
+ }
691
+ address++;
692
+ 7746: 21 96 adiw r28, 0x01 ; 1
693
+ putch(ch);
694
+ 7748: 18 d0 rcall .+48 ; 0x777a <putch>
695
+ } while (--length);
696
+ 774a: 01 50 subi r16, 0x01 ; 1
697
+ 774c: 10 40 sbci r17, 0x00 ; 0
698
+ 774e: 09 f0 breq .+2 ; 0x7752 <main+0x352>
699
+ 7750: b7 cf rjmp .-146 ; 0x76c0 <main+0x2c0>
700
+ 7752: ce 0c add r12, r14
701
+ 7754: df 1c adc r13, r15
702
+ 7756: 0e c0 rjmp .+28 ; 0x7774 <main+0x374>
703
+ }
704
+ }
705
+
706
+ /* Get device signature bytes */
707
+ else if(ch == STK_READ_SIGN) {
708
+ 7758: 85 37 cpi r24, 0x75 ; 117
709
+ 775a: 39 f4 brne .+14 ; 0x776a <main+0x36a>
710
+ // READ SIGN - return what Avrdude wants to hear
711
+ verifySpace();
712
+ 775c: 2d d0 rcall .+90 ; 0x77b8 <verifySpace>
713
+ putch(SIGNATURE_0);
714
+ 775e: 8e e1 ldi r24, 0x1E ; 30
715
+ 7760: 0c d0 rcall .+24 ; 0x777a <putch>
716
+ putch(SIGNATURE_1);
717
+ 7762: 85 e9 ldi r24, 0x95 ; 149
718
+ 7764: 0a d0 rcall .+20 ; 0x777a <putch>
719
+ putch(SIGNATURE_2);
720
+ 7766: 8f e0 ldi r24, 0x0F ; 15
721
+ 7768: 9f ce rjmp .-706 ; 0x74a8 <main+0xa8>
722
+ }
723
+ else if (ch == STK_LEAVE_PROGMODE) { /* 'Q' */
724
+ 776a: 81 35 cpi r24, 0x51 ; 81
725
+ 776c: 11 f4 brne .+4 ; 0x7772 <main+0x372>
726
+ // Adaboot no-wait mod
727
+ watchdogConfig(WATCHDOG_16MS);
728
+ 776e: 8c e0 ldi r24, 0x0C ; 12
729
+ 7770: 1d d0 rcall .+58 ; 0x77ac <watchdogConfig>
730
+ verifySpace();
731
+ }
732
+ else {
733
+ // This covers the response to commands like STK_ENTER_PROGMODE
734
+ verifySpace();
735
+ 7772: 22 d0 rcall .+68 ; 0x77b8 <verifySpace>
736
+ }
737
+ putch(STK_OK);
738
+ 7774: 80 e1 ldi r24, 0x10 ; 16
739
+ 7776: 01 d0 rcall .+2 ; 0x777a <putch>
740
+ 7778: 8a ce rjmp .-748 ; 0x748e <main+0x8e>
741
+
742
+0000777a <putch>:
743
+ }
744
+}
745
+
746
+void putch(char ch) {
747
+ 777a: 98 2f mov r25, r24
748
+#ifndef SOFT_UART
749
+ while (!(UART_SRA & _BV(UDRE0)));
750
+ 777c: 80 91 c0 00 lds r24, 0x00C0
751
+ 7780: 85 ff sbrs r24, 5
752
+ 7782: fc cf rjmp .-8 ; 0x777c <putch+0x2>
753
+ UART_UDR = ch;
754
+ 7784: 90 93 c6 00 sts 0x00C6, r25
755
+ [uartBit] "I" (UART_TX_BIT)
756
+ :
757
+ "r25"
758
+ );
759
+#endif
760
+}
761
+ 7788: 08 95 ret
762
+
763
+0000778a <getch>:
764
+ [uartBit] "I" (UART_RX_BIT)
765
+ :
766
+ "r25"
767
+);
768
+#else
769
+ while(!(UART_SRA & _BV(RXC0)))
770
+ 778a: 80 91 c0 00 lds r24, 0x00C0
771
+ 778e: 87 ff sbrs r24, 7
772
+ 7790: fc cf rjmp .-8 ; 0x778a <getch>
773
+ ;
774
+ if (!(UART_SRA & _BV(FE0))) {
775
+ 7792: 80 91 c0 00 lds r24, 0x00C0
776
+ 7796: 84 fd sbrc r24, 4
777
+ 7798: 01 c0 rjmp .+2 ; 0x779c <getch+0x12>
778
+}
779
+#endif
780
+
781
+// Watchdog functions. These are only safe with interrupts turned off.
782
+void watchdogReset() {
783
+ __asm__ __volatile__ (
784
+ 779a: a8 95 wdr
785
+ * don't care that an invalid char is returned...)
786
+ */
787
+ watchdogReset();
788
+ }
789
+
790
+ ch = UART_UDR;
791
+ 779c: 80 91 c6 00 lds r24, 0x00C6
792
+#ifdef LED_DATA_FLASH
793
+ LED_PORT ^= _BV(LED);
794
+#endif
795
+
796
+ return ch;
797
+}
798
+ 77a0: 08 95 ret
799
+
800
+000077a2 <uartDelay>:
801
+#if UART_B_VALUE > 255
802
+#error Baud rate too slow for soft UART
803
+#endif
804
+
805
+void uartDelay() {
806
+ __asm__ __volatile__ (
807
+ 77a2: 9a e2 ldi r25, 0x2A ; 42
808
+ 77a4: 9a 95 dec r25
809
+ 77a6: f1 f7 brne .-4 ; 0x77a4 <uartDelay+0x2>
810
+ 77a8: 08 95 ret
811
+ "1:dec r25\n"
812
+ "brne 1b\n"
813
+ "ret\n"
814
+ ::[count] "M" (UART_B_VALUE)
815
+ );
816
+}
817
+ 77aa: 08 95 ret
818
+
819
+000077ac <watchdogConfig>:
820
+ );
821
+}
822
+
823
+void watchdogConfig(uint8_t x) {
824
+#if 1
825
+ WDTCSR = _BV(WDCE) | _BV(WDE);
826
+ 77ac: e0 e6 ldi r30, 0x60 ; 96
827
+ 77ae: f0 e0 ldi r31, 0x00 ; 0
828
+ 77b0: 98 e1 ldi r25, 0x18 ; 24
829
+ 77b2: 90 83 st Z, r25
830
+ WDTCSR = x;
831
+ 77b4: 80 83 st Z, r24
832
+#endif
833
+}
834
+ 77b6: 08 95 ret
835
+
836
+000077b8 <verifySpace>:
837
+ do getch(); while (--count);
838
+ verifySpace();
839
+}
840
+
841
+void verifySpace() {
842
+ if (getch() != CRC_EOP) {
843
+ 77b8: e8 df rcall .-48 ; 0x778a <getch>
844
+ 77ba: 80 32 cpi r24, 0x20 ; 32
845
+ 77bc: 19 f0 breq .+6 ; 0x77c4 <verifySpace+0xc>
846
+ watchdogConfig(WATCHDOG_32MS); // shorten WD timeout
847
+ 77be: 8d e0 ldi r24, 0x0D ; 13
848
+ 77c0: f5 df rcall .-22 ; 0x77ac <watchdogConfig>
849
+ 77c2: ff cf rjmp .-2 ; 0x77c2 <verifySpace+0xa>
850
+ while (1) // and busy-loop so that WD causes
851
+ ; // a reset and app start.
852
+ }
853
+ putch(STK_INSYNC);
854
+ 77c4: 84 e1 ldi r24, 0x14 ; 20
855
+}
856
+ 77c6: d9 cf rjmp .-78 ; 0x777a <putch>
857
+ "ret\n"
858
+ ::[count] "M" (UART_B_VALUE)
859
+ );
860
+}
861
+
862
+void getNch(uint8_t count) {
863
+ 77c8: 1f 93 push r17
864
+
865
+000077ca <getNch>:
866
+ 77ca: 18 2f mov r17, r24
867
+ do getch(); while (--count);
868
+ 77cc: de df rcall .-68 ; 0x778a <getch>
869
+ 77ce: 11 50 subi r17, 0x01 ; 1
870
+ 77d0: e9 f7 brne .-6 ; 0x77cc <getNch+0x2>
871
+ verifySpace();
872
+ 77d2: f2 df rcall .-28 ; 0x77b8 <verifySpace>
873
+}
874
+ 77d4: 1f 91 pop r17
875
+ 77d6: 08 95 ret
876
+
877
+000077d8 <appStart>:
878
+
879
+void appStart(uint8_t rstFlags) {
880
+ // save the reset flags in the designated register
881
+ // This can be saved in a main program by putting code in .init0 (which
882
+ // executes before normal c init code) to save R2 to a global variable.
883
+ __asm__ __volatile__ ("mov r2, %0\n" :: "r" (rstFlags));
884
+ 77d8: 28 2e mov r2, r24
885
+
886
+ watchdogConfig(WATCHDOG_OFF);
887
+ 77da: 80 e0 ldi r24, 0x00 ; 0
888
+ 77dc: e7 df rcall .-50 ; 0x77ac <watchdogConfig>
889
+ __asm__ __volatile__ (
890
+ 77de: ec e0 ldi r30, 0x0C ; 12
891
+ 77e0: ff 27 eor r31, r31
892
+ 77e2: 09 94 ijmp
Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/optiboot_lgt8fx8p/pin_defs.h
... ...
@@ -0,0 +1,740 @@
1
+/*------------------------------------------------------------------------ */
2
+#if defined(__AVR_ATmega168__) || defined(__AVR_ATmega328P__) || defined(__AVR_ATmega88) || defined(__AVR_ATmega8__) || defined(__AVR_ATmega88__)
3
+/*------------------------------------------------------------------------ */
4
+
5
+/* Onboard LED is connected to pin PB5 in Arduino NG, Diecimila, and Duemilanove
6
+ */
7
+#if !defined(LED)
8
+#define LED B5
9
+#endif
10
+
11
+/* Ports for soft UART */
12
+#ifdef SOFT_UART
13
+#define UART_PORT PORTD
14
+#define UART_PIN PIND
15
+#define UART_DDR DDRD
16
+#define UART_TX_BIT 1
17
+#define UART_RX_BIT 0
18
+#endif
19
+#endif
20
+
21
+#if defined(__AVR_ATmega8__) || defined(__AVR_ATmega32__)
22
+ //Name conversion R.Wiersma
23
+ #define UCSR0A UCSRA
24
+ #define UDR0 UDR
25
+ #define UDRE0 UDRE
26
+ #define RXC0 RXC
27
+ #define FE0 FE
28
+ #define TIFR1 TIFR
29
+ #define WDTCSR WDTCR
30
+#endif
31
+#if defined(__AVR_ATmega32__)
32
+ #define WDCE WDTOE
33
+#endif
34
+
35
+/* Luminet support */
36
+/*------------------------------------------------------------------------ */
37
+#if defined(__AVR_ATtiny84__)
38
+/*------------------------------------------------------------------------ */
39
+/* Red LED is connected to pin PA4 */
40
+#if !defined(LED)
41
+#define LED A4
42
+#endif
43
+
44
+/* Ports for soft UART - left port only for now. TX/RX on PA2/PA3 */
45
+#ifdef SOFT_UART
46
+#define UART_PORT PORTA
47
+#define UART_PIN PINA
48
+#define UART_DDR DDRA
49
+#define UART_TX_BIT 2
50
+#define UART_RX_BIT 3
51
+#endif
52
+#endif
53
+
54
+/*------------------------------------------------------------------------ */
55
+/* Sanguino support (and other 40pin DIP cpus) */
56
+#if defined(__AVR_ATmega644P__) || defined(__AVR_ATmega1284P__) || defined(__AVR_ATmega32__)
57
+/*------------------------------------------------------------------------ */
58
+/* Onboard LED is connected to pin PB0 on Sanguino */
59
+#if !defined(LED)
60
+#define LED B0
61
+#endif
62
+
63
+/* Ports for soft UART */
64
+#ifdef SOFT_UART
65
+#define UART_PORT PORTD
66
+#define UART_PIN PIND
67
+#define UART_DDR DDRD
68
+#define UART_TX_BIT 1
69
+#define UART_RX_BIT 0
70
+#endif
71
+#endif
72
+
73
+/*------------------------------------------------------------------------ */
74
+/* Mega support */
75
+#if defined(__AVR_ATmega1280__)
76
+/*------------------------------------------------------------------------ */
77
+/* Onboard LED is connected to pin PB7 on Arduino Mega */
78
+#if !defined(LED)
79
+#define LED B7
80
+#endif
81
+
82
+/* Ports for soft UART */
83
+#ifdef SOFT_UART
84
+#define UART_PORT PORTE
85
+#define UART_PIN PINE
86
+#define UART_DDR DDRE
87
+#define UART_TX_BIT 1
88
+#define UART_RX_BIT 0
89
+#endif
90
+#endif
91
+
92
+/*
93
+ * ------------------------------------------------------------------------
94
+ * A bunch of macros to enable the LED to be specifed as "B5" for bit 5
95
+ * of port B, and similar.
96
+ */
97
+
98
+#define A0 0x100
99
+#define A1 0x101
100
+#define A2 0x102
101
+#define A3 0x103
102
+#define A4 0x104
103
+#define A5 0x105
104
+#define A6 0x106
105
+#define A7 0x107
106
+
107
+#define B0 0x200
108
+#define B1 0x201
109
+#define B2 0x202
110
+#define B3 0x203
111
+#define B4 0x204
112
+#define B5 0x205
113
+#define B6 0x206
114
+#define B7 0x207
115
+
116
+#define C0 0x300
117
+#define C1 0x301
118
+#define C2 0x302
119
+#define C3 0x303
120
+#define C4 0x304
121
+#define C5 0x305
122
+#define C6 0x306
123
+#define C7 0x307
124
+
125
+#define D0 0x400
126
+#define D1 0x401
127
+#define D2 0x402
128
+#define D3 0x403
129
+#define D4 0x404
130
+#define D5 0x405
131
+#define D6 0x406
132
+#define D7 0x407
133
+
134
+#define E0 0x500
135
+#define E1 0x501
136
+#define E2 0x502
137
+#define E3 0x503
138
+#define E4 0x504
139
+#define E5 0x505
140
+#define E6 0x506
141
+#define E7 0x507
142
+
143
+#define F0 0x600
144
+#define F1 0x601
145
+#define F2 0x602
146
+#define F3 0x603
147
+#define F4 0x604
148
+#define F5 0x605
149
+#define F6 0x606
150
+#define F7 0x607
151
+
152
+#define G0 0x700
153
+#define G1 0x701
154
+#define G2 0x702
155
+#define G3 0x703
156
+#define G4 0x704
157
+#define G5 0x705
158
+#define G6 0x706
159
+#define G7 0x707
160
+
161
+#define H0 0x800
162
+#define H1 0x801
163
+#define H2 0x802
164
+#define H3 0x803
165
+#define H4 0x804
166
+#define H5 0x805
167
+#define H6 0x806
168
+#define H7 0x807
169
+
170
+#define J0 0xA00
171
+#define J1 0xA01
172
+#define J2 0xA02
173
+#define J3 0xA03
174
+#define J4 0xA04
175
+#define J5 0xA05
176
+#define J6 0xA06
177
+#define J7 0xA07
178
+
179
+#define K0 0xB00
180
+#define K1 0xB01
181
+#define K2 0xB02
182
+#define K3 0xB03
183
+#define K4 0xB04
184
+#define K5 0xB05
185
+#define K6 0xB06
186
+#define K7 0xB07
187
+
188
+#define L0 0xC00
189
+#define L1 0xC01
190
+#define L2 0xC02
191
+#define L3 0xC03
192
+#define L4 0xC04
193
+#define L5 0xC05
194
+#define L6 0xC06
195
+#define L7 0xC07
196
+
197
+#if LED == B0
198
+#undef LED
199
+#define LED_DDR DDRB
200
+#define LED_PORT PORTB
201
+#define LED_PIN PINB
202
+#define LED PINB0
203
+#elif LED == B1
204
+#undef LED
205
+#define LED_DDR DDRB
206
+#define LED_PORT PORTB
207
+#define LED_PIN PINB
208
+#define LED PINB1
209
+#elif LED == B2
210
+#undef LED
211
+#define LED_DDR DDRB
212
+#define LED_PORT PORTB
213
+#define LED_PIN PINB
214
+#define LED PINB2
215
+#elif LED == B3
216
+#undef LED
217
+#define LED_DDR DDRB
218
+#define LED_PORT PORTB
219
+#define LED_PIN PINB
220
+#define LED PINB3
221
+#elif LED == B4
222
+#undef LED
223
+#define LED_DDR DDRB
224
+#define LED_PORT PORTB
225
+#define LED_PIN PINB
226
+#define LED PINB4
227
+#elif LED == B5
228
+#undef LED
229
+#define LED_DDR DDRB
230
+#define LED_PORT PORTB
231
+#define LED_PIN PINB
232
+#define LED PINB5
233
+#elif LED == B6
234
+#undef LED
235
+#define LED_DDR DDRB
236
+#define LED_PORT PORTB
237
+#define LED_PIN PINB
238
+#define LED PINB6
239
+#elif LED == B7
240
+#undef LED
241
+#define LED_DDR DDRB
242
+#define LED_PORT PORTB
243
+#define LED_PIN PINB
244
+#define LED PINB7
245
+
246
+#elif LED == C0
247
+#undef LED
248
+#define LED_DDR DDRC
249
+#define LED_PORT PORTC
250
+#define LED_PIN PINC
251
+#define LED PINC0
252
+#elif LED == C1
253
+#undef LED
254
+#define LED_DDR DDRC
255
+#define LED_PORT PORTC
256
+#define LED_PIN PINC
257
+#define LED PINC1
258
+#elif LED == C2
259
+#undef LED
260
+#define LED_DDR DDRC
261
+#define LED_PORT PORTC
262
+#define LED_PIN PINC
263
+#define LED PINC2
264
+#elif LED == C3
265
+#undef LED
266
+#define LED_DDR DDRC
267
+#define LED_PORT PORTC
268
+#define LED_PIN PINC
269
+#define LED PINC3
270
+#elif LED == C4
271
+#undef LED
272
+#define LED_DDR DDRC
273
+#define LED_PORT PORTC
274
+#define LED_PIN PINC
275
+#define LED PINC4
276
+#elif LED == C5
277
+#undef LED
278
+#define LED_DDR DDRC
279
+#define LED_PORT PORTC
280
+#define LED_PIN PINC
281
+#define LED PINC5
282
+#elif LED == C6
283
+#undef LED
284
+#define LED_DDR DDRC
285
+#define LED_PORT PORTC
286
+#define LED_PIN PINC
287
+#define LED PINC6
288
+#elif LED == C7
289
+#undef LED
290
+#define LED_DDR DDRC
291
+#define LED_PORT PORTC
292
+#define LED_PIN PINC
293
+#define LED PINC7
294
+
295
+#elif LED == D0
296
+#undef LED
297
+#define LED_DDR DDRD
298
+#define LED_PORT PORTD
299
+#define LED_PIN PIND
300
+#define LED PIND0
301
+#elif LED == D1
302
+#undef LED
303
+#define LED_DDR DDRD
304
+#define LED_PORT PORTD
305
+#define LED_PIN PIND
306
+#define LED PIND1
307
+#elif LED == D2
308
+#undef LED
309
+#define LED_DDR DDRD
310
+#define LED_PORT PORTD
311
+#define LED_PIN PIND
312
+#define LED PIND2
313
+#elif LED == D3
314
+#undef LED
315
+#define LED_DDR DDRD
316
+#define LED_PORT PORTD
317
+#define LED_PIN PIND
318
+#define LED PIND3
319
+#elif LED == D4
320
+#undef LED
321
+#define LED_DDR DDRD
322
+#define LED_PORT PORTD
323
+#define LED_PIN PIND
324
+#define LED PIND4
325
+#elif LED == D5
326
+#undef LED
327
+#define LED_DDR DDRD
328
+#define LED_PORT PORTD
329
+#define LED_PIN PIND
330
+#define LED PIND5
331
+#elif LED == D6
332
+#undef LED
333
+#define LED_DDR DDRD
334
+#define LED_PORT PORTD
335
+#define LED_PIN PIND
336
+#define LED PIND6
337
+#elif LED == D7
338
+#undef LED
339
+#define LED_DDR DDRD
340
+#define LED_PORT PORTD
341
+#define LED_PIN PIND
342
+#define LED PIND7
343
+
344
+#elif LED == E0
345
+#undef LED
346
+#define LED_DDR DDRE
347
+#define LED_PORT PORTE
348
+#define LED_PIN PINE
349
+#define LED PINE0
350
+#elif LED == E1
351
+#undef LED
352
+#define LED_DDR DDRE
353
+#define LED_PORT PORTE
354
+#define LED_PIN PINE
355
+#define LED PINE1
356
+#elif LED == E2
357
+#undef LED
358
+#define LED_DDR DDRE
359
+#define LED_PORT PORTE
360
+#define LED_PIN PINE
361
+#define LED PINE2
362
+#elif LED == E3
363
+#undef LED
364
+#define LED_DDR DDRE
365
+#define LED_PORT PORTE
366
+#define LED_PIN PINE
367
+#define LED PINE3
368
+#elif LED == E4
369
+#undef LED
370
+#define LED_DDR DDRE
371
+#define LED_PORT PORTE
372
+#define LED_PIN PINE
373
+#define LED PINE4
374
+#elif LED == E5
375
+#undef LED
376
+#define LED_DDR DDRE
377
+#define LED_PORT PORTE
378
+#define LED_PIN PINE
379
+#define LED PINE5
380
+#elif LED == E6
381
+#undef LED
382
+#define LED_DDR DDRE
383
+#define LED_PORT PORTE
384
+#define LED_PIN PINE
385
+#define LED PINE6
386
+#elif LED == E7
387
+#undef LED
388
+#define LED_DDR DDRE
389
+#define LED_PORT PORTE
390
+#define LED_PIN PINE
391
+#define LED PINE7
392
+
393
+#elif LED == F0
394
+#undef LED
395
+#define LED_DDR DDRF
396
+#define LED_PORT PORTF
397
+#define LED_PIN PINF
398
+#define LED PINF0
399
+#elif LED == F1
400
+#undef LED
401
+#define LED_DDR DDRF
402
+#define LED_PORT PORTF
403
+#define LED_PIN PINF
404
+#define LED PINF1
405
+#elif LED == F2
406
+#undef LED
407
+#define LED_DDR DDRF
408
+#define LED_PORT PORTF
409
+#define LED_PIN PINF
410
+#define LED PINF2
411
+#elif LED == F3
412
+#undef LED
413
+#define LED_DDR DDRF
414
+#define LED_PORT PORTF
415
+#define LED_PIN PINF
416
+#define LED PINF3
417
+#elif LED == F4
418
+#undef LED
419
+#define LED_DDR DDRF
420
+#define LED_PORT PORTF
421
+#define LED_PIN PINF
422
+#define LED PINF4
423
+#elif LED == F5
424
+#undef LED
425
+#define LED_DDR DDRF
426
+#define LED_PORT PORTF
427
+#define LED_PIN PINF
428
+#define LED PINF5
429
+#elif LED == F6
430
+#undef LED
431
+#define LED_DDR DDRF
432
+#define LED_PORT PORTF
433
+#define LED_PIN PINF
434
+#define LED PINF6
435
+#elif LED == F7
436
+#undef LED
437
+#define LED_DDR DDRF
438
+#define LED_PORT PORTF
439
+#define LED_PIN PINF
440
+#define LED PINF7
441
+
442
+#elif LED == G0
443
+#undef LED
444
+#define LED_DDR DDRG
445
+#define LED_PORT PORTG
446
+#define LED_PIN PING
447
+#define LED PING0
448
+#elif LED == G1
449
+#undef LED
450
+#define LED_DDR DDRG
451
+#define LED_PORT PORTG
452
+#define LED_PIN PING
453
+#define LED PING1
454
+#elif LED == G2
455
+#undef LED
456
+#define LED_DDR DDRG
457
+#define LED_PORT PORTG
458
+#define LED_PIN PING
459
+#define LED PING2
460
+#elif LED == G3
461
+#undef LED
462
+#define LED_DDR DDRG
463
+#define LED_PORT PORTG
464
+#define LED_PIN PING
465
+#define LED PING3
466
+#elif LED == G4
467
+#undef LED
468
+#define LED_DDR DDRG
469
+#define LED_PORT PORTG
470
+#define LED_PIN PING
471
+#define LED PING4
472
+#elif LED == G5
473
+#undef LED
474
+#define LED_DDR DDRG
475
+#define LED_PORT PORTG
476
+#define LED_PIN PING
477
+#define LED PING5
478
+#elif LED == G6
479
+#undef LED
480
+#define LED_DDR DDRG
481
+#define LED_PORT PORTG
482
+#define LED_PIN PING
483
+#define LED PING6
484
+#elif LED == G7
485
+#undef LED
486
+#define LED_DDR DDRG
487
+#define LED_PORT PORTG
488
+#define LED_PIN PING
489
+#define LED PING7
490
+
491
+#elif LED == H0
492
+#undef LED
493
+#define LED_DDR DDRH
494
+#define LED_PORT PORTH
495
+#define LED_PIN PINH
496
+#define LED PINH0
497
+#elif LED == H1
498
+#undef LED
499
+#define LED_DDR DDRH
500
+#define LED_PORT PORTH
501
+#define LED_PIN PINH
502
+#define LED PINH1
503
+#elif LED == H2
504
+#undef LED
505
+#define LED_DDR DDRH
506
+#define LED_PORT PORTH
507
+#define LED_PIN PINH
508
+#define LED PINH2
509
+#elif LED == H3
510
+#undef LED
511
+#define LED_DDR DDRH
512
+#define LED_PORT PORTH
513
+#define LED_PIN PINH
514
+#define LED PINH3
515
+#elif LED == H4
516
+#undef LED
517
+#define LED_DDR DDRH
518
+#define LED_PORT PORTH
519
+#define LED_PIN PINH
520
+#define LED PINH4
521
+#elif LED == H5
522
+#undef LED
523
+#define LED_DDR DDRH
524
+#define LED_PORT PORTH
525
+#define LED_PIN PINH
526
+#define LED PINH5
527
+#elif LED == H6
528
+#undef LED
529
+#define LED_DDR DDRH
530
+#define LED_PORT PORTH
531
+#define LED_PIN PINH
532
+#define LED PINH6
533
+#elif LED == H7
534
+#undef LED
535
+#define LED_DDR DDRH
536
+#define LED_PORT PORTH
537
+#define LED_PIN PINH
538
+#define LED PINH7
539
+
540
+#elif LED == J0
541
+#undef LED
542
+#define LED_DDR DDRJ
543
+#define LED_PORT PORTJ
544
+#define LED_PIN PINJ
545
+#define LED PINJ0
546
+#elif LED == J1
547
+#undef LED
548
+#define LED_DDR DDRJ
549
+#define LED_PORT PORTJ
550
+#define LED_PIN PINJ
551
+#define LED PINJ1
552
+#elif LED == J2
553
+#undef LED
554
+#define LED_DDR DDRJ
555
+#define LED_PORT PORTJ
556
+#define LED_PIN PINJ
557
+#define LED PINJ2
558
+#elif LED == J3
559
+#undef LED
560
+#define LED_DDR DDRJ
561
+#define LED_PORT PORTJ
562
+#define LED_PIN PINJ
563
+#define LED PINJ3
564
+#elif LED == J4
565
+#undef LED
566
+#define LED_DDR DDRJ
567
+#define LED_PORT PORTJ
568
+#define LED_PIN PINJ
569
+#define LED PINJ4
570
+#elif LED == J5
571
+#undef LED
572
+#define LED_DDR DDRJ
573
+#define LED_PORT PORTJ
574
+#define LED_PIN PINJ
575
+#define LED PINJ5
576
+#elif LED == J6
577
+#undef LED
578
+#define LED_DDR DDRJ
579
+#define LED_PORT PORTJ
580
+#define LED_PIN PINJ
581
+#define LED PINJ6
582
+#elif LED == J7
583
+#undef LED
584
+#define LED_DDR DDRJ
585
+#define LED_PORT PORTJ
586
+#define LED_PIN PINJ
587
+#define LED PINJ7
588
+
589
+#elif LED == K0
590
+#undef LED
591
+#define LED_DDR DDRK
592
+#define LED_PORT PORTK
593
+#define LED_PIN PINK
594
+#define LED PINK0
595
+#elif LED == K1
596
+#undef LED
597
+#define LED_DDR DDRK
598
+#define LED_PORT PORTK
599
+#define LED_PIN PINK
600
+#define LED PINK1
601
+#elif LED == K2
602
+#undef LED
603
+#define LED_DDR DDRK
604
+#define LED_PORT PORTK
605
+#define LED_PIN PINK
606
+#define LED PINK2
607
+#elif LED == K3
608
+#undef LED
609
+#define LED_DDR DDRK
610
+#define LED_PORT PORTK
611
+#define LED_PIN PINK
612
+#define LED PINK3
613
+#elif LED == K4
614
+#undef LED
615
+#define LED_DDR DDRK
616
+#define LED_PORT PORTK
617
+#define LED_PIN PINK
618
+#define LED PINK4
619
+#elif LED == K5
620
+#undef LED
621
+#define LED_DDR DDRK
622
+#define LED_PORT PORTK
623
+#define LED_PIN PINK
624
+#define LED PINK5
625
+#elif LED == K6
626
+#undef LED
627
+#define LED_DDR DDRK
628
+#define LED_PORT PORTK
629
+#define LED_PIN PINK
630
+#define LED PINK6
631
+#elif LED == K7
632
+#undef LED
633
+#define LED_DDR DDRK
634
+#define LED_PORT PORTK
635
+#define LED_PIN PINK
636
+#define LED PINK7
637
+
638
+#elif LED == L0
639
+#undef LED
640
+#define LED_DDR DDRL
641
+#define LED_PORT PORTL
642
+#define LED_PIN PINL
643
+#define LED PINL0
644
+#elif LED == L1
645
+#undef LED
646
+#define LED_DDR DDRL
647
+#define LED_PORT PORTL
648
+#define LED_PIN PINL
649
+#define LED PINL1
650
+#elif LED == L2
651
+#undef LED
652
+#define LED_DDR DDRL
653
+#define LED_PORT PORTL
654
+#define LED_PIN PINL
655
+#define LED PINL2
656
+#elif LED == L3
657
+#undef LED
658
+#define LED_DDR DDRL
659
+#define LED_PORT PORTL
660
+#define LED_PIN PINL
661
+#define LED PINL3
662
+#elif LED == L4
663
+#undef LED
664
+#define LED_DDR DDRL
665
+#define LED_PORT PORTL
666
+#define LED_PIN PINL
667
+#define LED PINL4
668
+#elif LED == L5
669
+#undef LED
670
+#define LED_DDR DDRL
671
+#define LED_PORT PORTL
672
+#define LED_PIN PINL
673
+#define LED PINL5
674
+#elif LED == L6
675
+#undef LED
676
+#define LED_DDR DDRL
677
+#define LED_PORT PORTL
678
+#define LED_PIN PINL
679
+#define LED PINL6
680
+#elif LED == L7
681
+#undef LED
682
+#define LED_DDR DDRL
683
+#define LED_PORT PORTL
684
+#define LED_PIN PINL
685
+#define LED PINL7
686
+
687
+#elif LED == A0
688
+#undef LED
689
+#define LED_DDR DDRA
690
+#define LED_PORT PORTA
691
+#define LED_PIN PINA
692
+#define LED PINA0
693
+#elif LED == A1
694
+#undef LED
695
+#define LED_DDR DDRA
696
+#define LED_PORT PORTA
697
+#define LED_PIN PINA
698
+#define LED PINA1
699
+#elif LED == A2
700
+#undef LED
701
+#define LED_DDR DDRA
702
+#define LED_PORT PORTA
703
+#define LED_PIN PINA
704
+#define LED PINA2
705
+#elif LED == A3
706
+#undef LED
707
+#define LED_DDR DDRA
708
+#define LED_PORT PORTA
709
+#define LED_PIN PINA
710
+#define LED PINA3
711
+#elif LED == A4
712
+#undef LED
713
+#define LED_DDR DDRA
714
+#define LED_PORT PORTA
715
+#define LED_PIN PINA
716
+#define LED PINA4
717
+#elif LED == A5
718
+#undef LED
719
+#define LED_DDR DDRA
720
+#define LED_PORT PORTA
721
+#define LED_PIN PINA
722
+#define LED PINA5
723
+#elif LED == A6
724
+#undef LED
725
+#define LED_DDR DDRA
726
+#define LED_PORT PORTA
727
+#define LED_PIN PINA
728
+#define LED PINA6
729
+#elif LED == A7
730
+#undef LED
731
+#define LED_DDR DDRA
732
+#define LED_PORT PORTA
733
+#define LED_PIN PINA
734
+#define LED PINA7
735
+
736
+#else
737
+#error -------------------------------------------
738
+#error Unrecognized LED name. Should be like "B5"
739
+#error -------------------------------------------
740
+#endif
Chip-cn-dat/LGT-dat/LGT8F328-SDK-DAT/optiboot_lgt8fx8p/stk500.h
... ...
@@ -0,0 +1,39 @@
1
+/* STK500 constants list, from AVRDUDE */
2
+#define STK_OK 0x10
3
+#define STK_FAILED 0x11 // Not used
4
+#define STK_UNKNOWN 0x12 // Not used
5
+#define STK_NODEVICE 0x13 // Not used
6
+#define STK_INSYNC 0x14 // ' '
7
+#define STK_NOSYNC 0x15 // Not used
8
+#define ADC_CHANNEL_ERROR 0x16 // Not used
9
+#define ADC_MEASURE_OK 0x17 // Not used
10
+#define PWM_CHANNEL_ERROR 0x18 // Not used
11
+#define PWM_ADJUST_OK 0x19 // Not used
12
+#define CRC_EOP 0x20 // 'SPACE'
13
+#define STK_GET_SYNC 0x30 // '0'
14
+#define STK_GET_SIGN_ON 0x31 // '1'
15
+#define STK_SET_PARAMETER 0x40 // '@'
16
+#define STK_GET_PARAMETER 0x41 // 'A'
17
+#define STK_SET_DEVICE 0x42 // 'B'
18
+#define STK_SET_DEVICE_EXT 0x45 // 'E'
19
+#define STK_ENTER_PROGMODE 0x50 // 'P'
20
+#define STK_LEAVE_PROGMODE 0x51 // 'Q'
21
+#define STK_CHIP_ERASE 0x52 // 'R'
22
+#define STK_CHECK_AUTOINC 0x53 // 'S'
23
+#define STK_LOAD_ADDRESS 0x55 // 'U'
24
+#define STK_UNIVERSAL 0x56 // 'V'
25
+#define STK_PROG_FLASH 0x60 // '`'
26
+#define STK_PROG_DATA 0x61 // 'a'
27
+#define STK_PROG_FUSE 0x62 // 'b'
28
+#define STK_PROG_LOCK 0x63 // 'c'
29
+#define STK_PROG_PAGE 0x64 // 'd'
30
+#define STK_PROG_FUSE_EXT 0x65 // 'e'
31
+#define STK_READ_FLASH 0x70 // 'p'
32
+#define STK_READ_DATA 0x71 // 'q'
33
+#define STK_READ_FUSE 0x72 // 'r'
34
+#define STK_READ_LOCK 0x73 // 's'
35
+#define STK_READ_PAGE 0x74 // 't'
36
+#define STK_READ_SIGN 0x75 // 'u'
37
+#define STK_READ_OSCCAL 0x76 // 'v'
38
+#define STK_READ_FUSE_EXT 0x77 // 'w'
39
+#define STK_READ_OSCCAL_EXT 0x78 // 'x'
SDK-dat/ISP-dat/ISP-dat.md
... ...
@@ -0,0 +1,16 @@
1
+
2
+# ISP-dat
3
+
4
+
5
+- [[programmer-socket-dat]]
6
+
7
+- [[CH55x-dat]]
8
+
9
+- [[LGT8F328-SDK-DAT]]
10
+
11
+
12
+
13
+
14
+## ref
15
+
16
+- [[SDK-dat]]
... ...
\ No newline at end of file
board-series-dat/programmer-socket-dat/programmer-socket-dat.md
... ...
@@ -0,0 +1,12 @@
1
+
2
+# programmer-socket-dat
3
+
4
+- [[CCO3626-dat]] - [[CCO3627-dat]] - [[CCO3628-dat]] - [[CCO3629-dat]] - [[DPR1016-dat]] - [[programmer-socket-dat]]
5
+
6
+https://www.electrodragon.com/product-category/modules/programmer/ic-socket-programmer/
7
+
8
+
9
+
10
+## ref
11
+
12
+- [[CCO3527-dat]]
... ...
\ No newline at end of file