Chip-dat/altera-dat/altera-dat.md
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# altera-dat
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+
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+
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+- [[CPLD-dat]] - [[FPGA-dat]] - [[altera-dat]]
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+
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+
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+
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+
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+
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hand book MAX II - [[max2_mii5v1.pdf]]
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- [[MAX10-dat]]
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+## EPM7192
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+
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+
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+EPM7192SQI160-10 - IC CPLD 192MC 10NS 160QFP
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+
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+Features...
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+- ■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture
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+- ■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
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+ - – ISP circuitry compatible with IEEE Std. 1532
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+- ■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
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+- ■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
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+- ■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2)
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+- ■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
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+- ■ PCI-compliant devices available
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+
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+
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+https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/987/MAX7000_Family_DS.pdf
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+
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+
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+
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## demo code
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- [[led_water(570).zip]]
Chip-dat/xilinx-dat/ZYNQ-dat/ZYNQ-dat.md
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# ZYNQ-dat
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+- [[CPLD-dat]] - [[AMD-dat]] - [[Xilinx-dat]] - [[ZYNQ-dat]]
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+
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+
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Zynq UltraScale+ RFSoC
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FPGA RF Soc - XCZU48DR-2FSVG1517I
Tech-dat/MCU-dat/CPLD-dat/cpld-dat.md
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# cpld dat
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-- [[XILINX-dat]]
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+- [[CPLD-dat]] - [[AMD-dat]] - [[Xilinx-dat]] - [[ZYNQ-dat]]
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+
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+- [[CPLD-dat]] - [[FPGA-dat]] - [[altera-dat]]
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+
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+
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+
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+
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## boards
Tech-dat/MCU-dat/FPGA-dat/FPGA-dat.md
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# FPGA-dat
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+
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+- [[CPLD-dat]] - [[AMD-dat]] - [[Xilinx-dat]] - [[ZYNQ-dat]]
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+
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+- [[CPLD-dat]] - [[FPGA-dat]] - [[altera-dat]]
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+
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+
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+
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+
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+
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- [[xilinx-dat]]
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- [[USB-Blaster-dat]] - [[CH552-dat]]