PCB-dat/PCB-dat/4-layer-dat/4-layer-dat.md
... ...
@@ -0,0 +1,71 @@
1
+
2
+# 4-layer-dat
3
+
4
+## specs
5
+
6
+- inner layer == 0.5 oz
7
+
8
+
9
+## lamination
10
+
11
+The typical lamination order for a 4-layer PCB is:
12
+
13
+- Top Layer: Signal layer
14
+- Inner Layer 1: Power plane (e.g., VCC or GND)
15
+- Inner Layer 2: Ground plane (e.g., GND or VCC)
16
+- Bottom Layer: Signal layer
17
+
18
+### lamination order
19
+
20
+"4-layer PCB stack-up:
21
+
22
+- Top Layer: Signal
23
+- Inner Layer 1: Power (VCC)
24
+- Inner Layer 2: Ground (GND)
25
+- Bottom Layer: Signal
26
+
27
+Please follow this lamination order for manufacturing."
28
+
29
+### šŸ”„ Typical 4-Layer Stackup (Example)
30
+
31
+| Layer | Purpose |
32
+|-------|-----------------------------|
33
+| L1 | Signal (High-speed / Logic) |
34
+| L2 | Ground Plane |
35
+| L3 | Power Plane (3.3V, etc.) |
36
+| L4 | Signal (Slower or routing) |
37
+
38
+This stackup helps with:
39
+- Good **signal integrity** (especially PCIe or USB lines)
40
+- **Controlled impedance** for high-speed routing
41
+- **Noise reduction** and **EMI compliance**
42
+
43
+---
44
+
45
+## āš™ļø Why Use 4 Layers?
46
+
47
+| Reason | Explanation |
48
+|-------------------------------|---------------------------------------------|
49
+| Signal integrity | PCIe and USB need impedance control |
50
+| Power distribution | Separate plane ensures clean power |
51
+| Ground return path | Reduces EMI / crosstalk |
52
+| Compact routing | Easier routing in tight Mini PCIe space |
53
+
54
+---
55
+
56
+## šŸ”§ Considerations
57
+
58
+- Use **controlled impedance** (50Ī© for USB, 85Ī© diff for PCIe)
59
+- Ensure **gold fingers** are ENIG plated and follow **Mini PCIe spec**
60
+- Route high-speed signals on **L1 and L4**, with ground under them
61
+- Place components only on the **top layer**, per Mini PCIe mechanical spec
62
+- Follow PCI-SIG or Mini PCIe spec for **connector layout** and **keep-outs**
63
+
64
+
65
+## ref
66
+
67
+- [[PCB-dat]]
68
+
69
+- [[camera-dat]]
70
+
71
+- [[c]]
... ...
\ No newline at end of file
PCB-dat/PCB-dat/EDA-dat/EDA-dat.md
... ...
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1
+
2
+# EDA-dat.md
3
+
4
+- [[eaglecad-dat]]
5
+
6
+- [[kicad-dat]]
7
+
8
+- [[LCEDA]]
9
+
10
+- [[altium-designer-dat]]
11
+
12
+- [[protel-dat]]
13
+
14
+
15
+
16
+
17
+
18
+## ref
19
+
20
+- [[PCB-dat]] - [[PCBA-dat]] - [[EDA-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-dat/EDA-dat/eaglecad-dat/2024-04-02-14-24-27.png
... ...
Binary files /dev/null and b/PCB-dat/PCB-dat/EDA-dat/eaglecad-dat/2024-04-02-14-24-27.png differ
PCB-dat/PCB-dat/EDA-dat/eaglecad-dat/2024-04-02-14-24-54.png
... ...
Binary files /dev/null and b/PCB-dat/PCB-dat/EDA-dat/eaglecad-dat/2024-04-02-14-24-54.png differ
PCB-dat/PCB-dat/EDA-dat/eaglecad-dat/eagle-simulation-dat/eagle-simulation-dat.md
... ...
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1
+
2
+# eagle-simulation-dat
3
+
4
+
5
+## add model card for spice, examples
6
+
7
+D:\EAGLE 9.6.2\examples\spice\examples\OPAMP.mdl
8
+
9
+
10
+
11
+## The model card does not include the required .MODEL line, please check your model.
12
+
13
+The model card cannot include subcircuit definitions.
14
+
15
+ * BASIC OP AMP MODEL
16
+ * Device Pins In+ In- vdd vss Vout
17
+ * vdd vss unused in this model!!
18
+ .SUBCKT opamp 1 2 vdd vss vout
19
+ *
20
+ * INPUT
21
+ RIN 1 2 1e9
22
+ *
23
+ * AMPLIFIER STAGE: GAIN, POLE, SLEW
24
+ * Aol=10000, fu=1000000 Hz
25
+ G1 0 10 VALUE = { 1e-2 * V(1,2) }
26
+ R1 10 0 1e6
27
+ C1 10 0 1.59e-9
28
+ *
29
+ * 2ND POLE
30
+ G2 0 20 10 0 1e-6
31
+ R2 20 0 1e6
32
+ C2 20 0 3.3e-14
33
+ *
34
+ * 3RD POLE
35
+ G3 0 30 20 0 1e-6
36
+ R3 30 0 1e6
37
+ C3 30 0 3.3e-14
38
+ *
39
+ * OUTPUT STAGE
40
+ EBUFFER 80 0 30 0 1
41
+ ROUT 80 vout 100
42
+ .ENDS opamp
... ...
\ No newline at end of file
PCB-dat/PCB-dat/EDA-dat/eaglecad-dat/eaglecad-dat.md
... ...
@@ -0,0 +1,28 @@
1
+
2
+# eagle-CAD-dat
3
+
4
+- https://github.com/Edragon/Eagle-CAD-dat
5
+- ~~https://github.com/Edragon/CAD-Eagle-part~~
6
+
7
+
8
+## Tips
9
+
10
+### oval, or oblong shapes
11
+
12
+Unfortunately there is still no option for creating a plated slot in the library editor with the ease you can an SMD or PAD. However, you can do as @millingm suggested or the variation I prefer which is a PAD on each end of the slot and then draw each of the inner/outer layer pad areas with a polygon on each of the 16 routing layers. The also draw the slot as a line on the Milling layer. You end up with something like this in your library:
13
+
14
+![](2024-04-02-14-24-27.png)
15
+
16
+And when it is in the board you end up with:
17
+
18
+![](2024-04-02-14-24-54.png)
19
+
20
+https://forums.autodesk.com/t5/eagle-forum/slotted-pads/td-p/7487203
21
+
22
+
23
+
24
+
25
+
26
+## ref
27
+
28
+- [[eagle-cad]]
... ...
\ No newline at end of file
PCB-dat/PCB-dat/EDA-dat/fritzing.org-dat/fritzing.org-dat.md
... ...
@@ -0,0 +1,4 @@
1
+
2
+# fritzing.org-dat
3
+
4
+https://fritzing.org/
... ...
\ No newline at end of file
PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-dat.md
... ...
@@ -0,0 +1,48 @@
1
+
2
+# kicad-dat
3
+
4
+- lib ꗧē‰ˆ ē¬¦å·ę–‡ä»¶
5
+
6
+- [[kicad-workflow-dat]] - [[kicad-plugin-dat]] - [[kicad-shortcuts-dat]]
7
+
8
+- [[kicad-lib-dat]] - [[kicad-data-dat]] - [[kicad-setup-dat]]
9
+
10
+- [[kicad-symbol-dat]] - [[kicad-footprint-dat]]
11
+
12
+- [[kicad-simulation-dat]]
13
+
14
+
15
+
16
+
17
+## Glossary
18
+
19
+### DCM = documentation file
20
+
21
+If you donā€™t copy the DCM files, you will lose the documentation. I believe that the library will otherwise still function but donā€™t quote me on that; you can try it and find out.
22
+
23
+(maybe goes with out saying, but in v6 you only have a single .kicad_sym file which contains all the info)
24
+
25
+### .mod
26
+** Files that end in ā€œ.kicad_modā€, typically in folders with names that end in ā€œ.prettyā€, are the 2014(?) version of modules (a KiCad ā€œmoduleā€ is called a ā€œfootprintā€ or a ā€œdecalā€ in other CAD software), one footprint per file, lots of files in the entire ā€œ.prettyā€ library.*
27
+
28
+** Files that end in ā€œ.modā€ are module libraries (a KiCad ā€œmoduleā€ is called a ā€œfootprintā€ or a ā€œdecalā€ in other CAD software)*
29
+
30
+
31
+## Tips
32
+
33
+### Renaming all associated netnames
34
+
35
+https://gitlab.com/kicad/code/kicad/-/issues/5151
36
+
37
+TIL that Find/Replace is for more than just text (like any other tool)
38
+
39
+alt ctrl F
40
+
41
+
42
+## Features
43
+
44
+- [[reverse-engineering-dat]]
45
+
46
+## ref
47
+
48
+- [[kicad]]
... ...
\ No newline at end of file
PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-data-dat.md
... ...
@@ -0,0 +1,28 @@
1
+
2
+# kicad-data-dat.md
3
+
4
+## labels
5
+
6
+https://t.me/electrodragon3/253
7
+
8
+copy mutiple labels from kicad, paste here, and can be copied back once edition done.
9
+
10
+(label "DAI" (at 100.33 392.43 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "0cabd4dc-e713-45de-8364-1815a0e2f378"))
11
+(label "DFC" (at 100.33 420.37 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "148c8dd8-9aee-4311-8806-46c0dfb928be"))
12
+(label "DDC" (at 100.33 410.21 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "17577330-cb40-4248-bedd-2e3030fd3781"))
13
+(label "DEI" (at 100.33 412.75 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "b5aa1c90-3cf0-44b0-85fe-720de64bc716"))
14
+(label "DAC" (at 100.33 394.97 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "b69ab755-8299-436c-9a2b-c757923ef6f8"))
15
+(label "DEC" (at 100.33 415.29 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "a67ffca3-b51e-4bda-b76d-416d5275c15b"))
16
+(label "DCC" (at 100.33 405.13 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "a113b754-b329-46c5-98f9-d549d4fd6091"))
17
+(label "DFI" (at 100.33 417.83 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "55acfa6a-5920-4eca-a678-1d1233d27332"))
18
+(label "DHI" (at 100.33 427.99 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "5534b9d1-6bf9-4427-950f-85a4b775e475"))
19
+(label "DHC" (at 100.33 430.53 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "9784cdd3-6225-40f0-aa0e-383216de333b"))
20
+(label "DDI" (at 100.33 407.67 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "c78290c8-0cf7-4e5b-98af-767101b1ea27"))
21
+(label "DBI" (at 100.33 397.51 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "cf988d22-b3b9-4dba-a82d-ff2d0943401e"))
22
+(label "DGC" (at 100.33 425.45 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "bee3fd6d-1ea9-4468-82e5-83bb127095ec"))
23
+(label "DCI" (at 100.33 402.59 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "d6c63f27-b435-456b-b720-0dadbd0c27b4"))
24
+(label "DBC" (at 100.33 400.05 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "e11f0e4c-b5ae-4f6b-abe2-c4ac16cbf189"))
25
+(label "DGI" (at 100.33 422.91 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "e720d05b-ef4d-4914-a12f-a25d7dfec183"))
26
+
27
+
28
+
PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-lib-dat/2025-04-29-15-16-53.png
... ...
Binary files /dev/null and b/PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-lib-dat/2025-04-29-15-16-53.png differ
PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-lib-dat/kicad-footprint-dat.md
... ...
@@ -0,0 +1,80 @@
1
+
2
+# kicad-footprint-dat.md
3
+
4
+- [[kicad-symbol-dat]] - [[kicad-pcb-dat]]
5
+
6
+## custom build footprint guide
7
+
8
+![](2025-04-29-15-16-53.png)
9
+
10
+## common used global library
11
+
12
+- Connector_pinheader
13
+- Connector_Wire
14
+ - SolderingWirePad_1x01_SMD_1x2mm
15
+- Connector_USB
16
+ - USB_C_Receptacle_G-Switch_GT-USB-7010ASV
17
+ - USB_A_CNCTech_1001-011-01101_Horizontal == [[USB-A-dat]]
18
+- MountingHole
19
+ - MountingHole_3.2mm_M3
20
+- Package_SO
21
+ - SOIC-8_5.3x5.3mm_P1.27mm
22
+ - SOIC-16_10.3x7.5mm_P1.27mm
23
+ - SOP-8_3.9x4.9mm_P1.27mm
24
+ - SOP-8_3.76x4.96mm_P1.27mm
25
+
26
+
27
+
28
+## other collections
29
+
30
+[Kicad_FPC_board_ends](https://github.com/mikeWShef/Kicad_FPC_board_ends)
31
+
32
+
33
+
34
+## QA
35
+
36
+how to import or open kicad .mod file?
37
+
38
+
39
+`.mod` is KiCadā€™s **legacy footprint library** format (preā€“KiCad 5).
40
+
41
+Modern KiCad uses `.kicad_mod` files inside `.pretty` folders.
42
+
43
+
44
+### Method 1 ā€” Import with Library Wizard (Legacy Loader)
45
+
46
+1. Open **PCB Editor**.
47
+2. Go to **Preferences ā†’ Manage Footprint Libraries**.
48
+3. Click **Append with Wizard** (or **Add existing library**).
49
+4. Select your **`.mod`** file.
50
+5. Finish the wizard ā†’ the legacy library is added and usable.
51
+
52
+
53
+### Method 2 ā€” Convert to Modern `.pretty` Library (Recommended)
54
+
55
+Use KiCadā€™s converter to create a modern library:
56
+
57
+~~kicad-footprint2pretty old_library.mod new_library.pretty~~
58
+
59
+**footprint editor -> import -> select .mod file**
60
+
61
+Result: new_library.pretty/ containing individual *.kicad_mod footprints.
62
+
63
+Then in PCB Editor: Preferences ā†’ Manage Footprint Libraries ā†’ Add the new .pretty path.
64
+
65
+### Method 3 ā€” Use Older KiCad to Re-save
66
+
67
+Open the .mod in KiCad v4 (or compatible).
68
+
69
+Export/Save footprints to a .pretty library, then add it in current KiCad.
70
+
71
+Tips
72
+Keep original .mod as a backup.
73
+
74
+After conversion, verify pad sizes, layers, and 3D model links.
75
+
76
+
77
+
78
+## ref
79
+
80
+- [[kicad-symbol-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-lib-dat/kicad-lib-dat.md
... ...
@@ -0,0 +1,20 @@
1
+
2
+# kicad-lib.md
3
+
4
+
5
+
6
+## common used lib
7
+
8
+- power
9
+ - +5V
10
+ - GND
11
+- Device
12
+ - R == resistor
13
+ - LED
14
+
15
+
16
+## simulation
17
+
18
+- simulation_SPICE
19
+ - vdc
20
+
PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-lib-dat/kicad-symbol-dat.md
... ...
@@ -0,0 +1,45 @@
1
+
2
+# kicad-symbol-dat.md
3
+
4
+- [[kicad-footprint-dat]]
5
+
6
+## custom build symbol guide
7
+
8
+## common used global symbol A to Z
9
+
10
+- Amplifier_Current
11
+- Amlifier_Operational
12
+- Battery_Management
13
+ - TP4056-42-ESOP8 == [[TP4056-dat]]
14
+- Connector
15
+ - Conn_01x01_Pin
16
+ - USB_C_Plug
17
+ - USB_A == type A plugger == [[USB-A-dat]]
18
+- Connector_generic_MountingPin
19
+- Device
20
+ - C == [[capacitor-dat]]
21
+ - R == [[resistor-dat]]
22
+ - LED == [[LED-dat]]
23
+- interface_USB
24
+ - CH340N
25
+- Jumper
26
+ - SolderingJumper
27
+- Mechanicals
28
+ - MountingHole
29
+- MCU_Microchip_ATTiny
30
+- Power
31
+ - GND
32
+- RF_Module
33
+- Switch
34
+ - SW_DPDP_2x
35
+- Interface_Optical
36
+ - SFP+
37
+ - SFP
38
+
39
+## ref
40
+
41
+- [[kicad-footprint-dat]]
42
+
43
+- [[USB-dat]]
44
+
45
+
PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-plugin-dat/2024-09-22-03-39-54.png
... ...
Binary files /dev/null and b/PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-plugin-dat/2024-09-22-03-39-54.png differ
PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-plugin-dat/kicad-plugin-dat.md
... ...
@@ -0,0 +1,61 @@
1
+
2
+# kicad-plugin
3
+
4
+## testing
5
+
6
+- interactive html bom
7
+- pcb-action-tools
8
+- board2pdf
9
+- kikit
10
+- kibuzzard - custom font label generator
11
+- archive 3d models
12
+- aisler push for kicad
13
+- place footprints
14
+- replicate layout
15
+- round tracks
16
+- save/restore layout
17
+- fabrication toolkit
18
+- stretch
19
+- keyboard footprints placer
20
+- kimotor
21
+- pinout generator
22
+- transform it
23
+- oktizer action plugin
24
+- bulk hide silkscreen designators
25
+- impart gui for kicad
26
+- gerber to order
27
+- hide references
28
+- KLEPlacement
29
+- hierarchicalPCB
30
+- sparkfun kicad panelizer
31
+- parasitics
32
+- PCBway fabrication toolkit
33
+- kimesh
34
+- PCB coil generator
35
+- sparkfun kicad CAMer
36
+- kicad coil generator
37
+- Git plugin
38
+- thermal relief via
39
+- pcb2blender
40
+- KiVar
41
+- Swapstubs
42
+- KiCAD testpoints
43
+- cut tracks at line
44
+- HQ PCB
45
+- parts placer
46
+- set hole diameter
47
+- via patterns
48
+- schematic blocks plug-in
49
+
50
+
51
+## useful
52
+
53
+- freerouting - https://hackaday.com/2023/04/14/kicad-autorouting-made-easy/
54
+
55
+![](2024-09-22-03-39-54.png)
56
+
57
+
58
+## install java TLS version
59
+
60
+- https://adoptium.net/download/
61
+
PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-setup-dat.md
... ...
@@ -0,0 +1,42 @@
1
+
2
+# kicad-setup-dat.md
3
+
4
+installation == D:\Program Files\KiCad\9.0\bin
5
+
6
+## preferences
7
+
8
+configure paths
9
+
10
+| Name | Path |
11
+| ----------------------- | -------------------------------------------------- |
12
+| KICAD9_3DMODEL_DIR | D:\Program Files\KiCad\9.0\share\kicad\3dmodels\ |
13
+| KICAD9_3RD_PARTY | D:\HE2\Documents\KiCad\9.0\3rdparty |
14
+| KICAD9_DESIGN_BLOCK_DIR | D:\Program Files\KiCad\9.0\share\kicad\blocks\ |
15
+| KICAD9_FOOTPRINT_DIR | D:\Program Files\KiCad\9.0\share\kicad\footprints\ |
16
+| KICAD9_SYMBOL_DIR | D:\Program Files\KiCad\9.0\share\kicad\symbols\ |
17
+| KICAD9_TEMPLATE _DIR | D:\Program Files\KiCad\9.0\share/kicad/template |
18
+| KICAD_USER_TEMPLATE_DIR | D:\HE2\Documents\KiCad\9.0\template\ |
19
+
20
+
21
+## Available path substitutions:
22
+
23
+| variables | paths |
24
+| -------------------- | ----------------------------------------------- |
25
+| ${KICAD9_SYMBOL_DIR} | D:\Program Files\KiCad\9.0\share\kicad\symbols\ |
26
+| ${KIPRJMOD} | D:\Dropbox\PCB\kicad\proj\USB-HFBR |
27
+
28
+
29
+
30
+
31
+## Common Error
32
+
33
+
34
+### Software Stuck // no respone // freezing
35
+
36
+- This is a IME problem, if you use any other languages input methods, switch back to default ENG
37
+
38
+
39
+## ref
40
+
41
+- [[kicad-dat]]
42
+
PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-shortcuts-dat/kicad-shortcuts-dat.md
... ...
@@ -0,0 +1,6 @@
1
+
2
+# kicad-shortcuts-dat
3
+
4
+A == symbol
5
+
6
+
PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-simulation-dat/2025-03-18-14-46-38.png
... ...
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PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-simulation-dat/kicad-simulation-dat.md
... ...
@@ -0,0 +1,107 @@
1
+
2
+# kicad-simulation-dat
3
+
4
+- [[LM358-dat]]
5
+
6
+- [[EDA-simulation-dat]]
7
+
8
+## Import SPICE model
9
+
10
+SPICE model from file (*.lib, *.sub or *ibs)
11
+
12
+## custom build
13
+
14
+LED
15
+
16
+I opened their ā€œTools and supportā€ tab, underneath I, found a design resources tab. (figure 1)
17
+
18
+![](2025-03-18-14-49-30.png)
19
+
20
+Underneath design resources they asked for the type of document, I chose ā€œSimulation Modelsā€ (figure 2)
21
+
22
+I searched for the part by name: ā€œBC547ā€. We want the library, so we choose ā€œBC547 Lib Modelā€ and downloaded it. (figure 3)
23
+
24
+
25
+OP-Amp
26
+
27
+![](2025-03-18-15-22-45.png)
28
+
29
+## setup
30
+
31
+[VDC](https://ngspice.sourceforge.io/docs/ngspice-html-manual/manual.xhtml#sec_Independent_Sources_for)
32
+
33
+
34
+### LED
35
+
36
+![](2025-03-18-14-46-38.png)
37
+LEDs are a bit trickier in the fact that modeling them requires some knowledge about their parameters and curve-fitting. So, to model them I just looked up ā€œLED ngspiceā€.
38
+
39
+I found multiple people posting their ā€œLED modelsā€ and I decided to go with this
40
+
41
+ā€œ *Typ RED GaAs LED: Vf=1.7V Vr=4V If=40mA trr=3uS .MODEL LED1 D (IS=93.2P RS=42M N=3.73 BV=4 IBV=10U + CJO=2.97P VJ=.75 M=.333 TT=4.32U)?ā€
42
+
43
+
44
+## download
45
+
46
+
47
+[Simulation examples for KiCad8/KiCad9/Eeschema/ngspice](https://forum.kicad.info/t/simulation-examples-for-kicad8-kicad9-eeschema-ngspice/45546)
48
+
49
+- Generic symbols with generic models, see intro4
50
+- Another 555 circuit example
51
+
52
+[github collections](https://github.com/labtroll/KiCad-Simulations)
53
+
54
+[simulation-examples-for-kicad-eeschema-ngspice](https://forum.kicad.info/t/simulation-examples-for-kicad-eeschema-ngspice/34443/4)
55
+
56
+
57
+## tuto kicad 9
58
+
59
+[ref tutorial](https://ngspice.sourceforge.io/ngspice-eeschema.html#OpAmp)
60
+
61
+
62
+### simple - voltage ladder
63
+
64
+![](2025-03-18-16-04-42.png)
65
+
66
+
67
+### AC Since - RC Ladder
68
+
69
+Schematic Setup
70
+
71
+![](2025-03-18-15-39-01.png)
72
+
73
+SPICE Simulator
74
+
75
+![](2025-03-18-15-35-42.png)
76
+
77
+### Inverting Amplifier - Transient Analysis
78
+
79
+https://www.youtube.com/watch?v=6YvECTfwVOw
80
+
81
+
82
+## tuto
83
+
84
+https://www.instructables.com/Simulating-a-KiCad-Circuit/
85
+
86
+3Y ago
87
+https://www.youtube.com/watch?v=pCQ4MUyQjx0
88
+
89
+https://www.kicad.org/discover/spice/
90
+
91
+simple transistor build and simulate
92
+https://www.woolseyworkshop.com/2019/07/01/performing-a-circuit-simulation-in-kicad/
93
+
94
+
95
+## OPA1641
96
+
97
+- need to fix the pin assignment
98
+- [great tuto here](https://www.youtube.com/watch?v=Wg7uSs4J_0U)
99
+
100
+Transient Analysis == step 10u / final 10m
101
+
102
+![](2025-03-18-18-18-23.png)
103
+
104
+
105
+## ref
106
+
107
+- [[kicad-dat]] - [[voltage-divider-dat]]
... ...
\ No newline at end of file
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PCB-dat/PCB-dat/EDA-dat/kicad-dat/kidcad-workflow-dat/kicad-pcb-dat/kicad-pcb-dat.md
... ...
@@ -0,0 +1,108 @@
1
+
2
+# kicad-pcb-dat
3
+
4
+## import from other template projects
5
+
6
+pre-defined file: D:\Program Files\KiCad\8.0\share\kicad\template\Arduino_Nano
7
+
8
+- DRC rules = design rules constrains
9
+- teardrop defaults
10
+
11
+
12
+
13
+![](2024-10-08-19-42-52.png)
14
+
15
+
16
+
17
+### update into PCB
18
+
19
+
20
+
21
+- switch to PCB
22
+- update from PCB
23
+- fix errors
24
+- update PCB
25
+- layout it
26
+
27
+![](2024-09-18-01-43-12.png)
28
+
29
+![](2024-09-18-01-43-55.png)
30
+
31
+
32
+
33
+
34
+## PCB layout
35
+
36
+- autoroute - by [[kicad-plugin-dat]]
37
+
38
+
39
+
40
+## PCB Info
41
+
42
+commom layers
43
+
44
+| layers | explain | CN |
45
+| -------------- | ------------------ | ------ |
46
+| edge.cuts | board edge layer | č¾¹ę”†å±‚ |
47
+| F/B Silkscreen | Silkscreen layer | äøå°å±‚ |
48
+| F/B Mask | Mask layer | 阻ē„Šå±‚ |
49
+| F/B Paste | solder Paste layer | é””č†å±‚ |
50
+| F/B Cu | copper layer | 铜ē®”层 |
51
+
52
+* F for front and B for back
53
+
54
+## PCB init setup
55
+
56
+![](2023-12-11-00-04-17.png)
57
+
58
+- ē½‘ē»œēŗæ宽
59
+- 钻孔å°ŗåÆø
60
+- ē½‘ę ¼ 1.0 mm
61
+- ē¼©ę”¾
62
+
63
+## Layout setup
64
+
65
+Simply Only use Trace x.CU, Silkscreen layer x.Silkscreen, and Edge.Cuts
66
+
67
+![](2025-04-29-16-22-13.png)
68
+
69
+
70
+## routing PCB
71
+
72
+![](2025-04-29-16-11-14.png)
73
+
74
+![](2025-04-29-16-11-39.png)
75
+
76
+
77
+## Modify PCB
78
+
79
+
80
+## Filled Zones (ground pour)
81
+
82
+Edit - Fill All Zones (B or Ctrl+B)
83
+
84
+
85
+### Optimized the Text
86
+
87
+Optimize the text size of the desginators
88
+
89
+![](2025-05-12-13-02-00.png)
90
+
91
+text width and height 0.6 mm
92
+
93
+## export gerber
94
+
95
+output folder
96
+
97
+ for the current folder == ./
98
+ for the sub folder "gerber" in current folder == ./gerber
99
+
100
+
101
+## export info
102
+
103
+
104
+layer
105
+- x.Mask
106
+- x.Fab
107
+- Edge.Cuts
108
+![alt text](95e854b5209f226b023ebe7765500e9.png)
... ...
\ No newline at end of file
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PCB-dat/PCB-dat/EDA-dat/kicad-dat/kidcad-workflow-dat/kicad-sch-dat/kicad-sch-dat.md
... ...
@@ -0,0 +1,35 @@
1
+
2
+# kicad-sch-dat
3
+
4
+
5
+
6
+### add symbol
7
+
8
+- search based on components type and footprint
9
+
10
+![](2024-10-06-16-39-37.png)
11
+
12
+- ctrl+D duplicate the symbol
13
+
14
+- [[kicad-symbol-dat]]
15
+
16
+### mutiple assign the value
17
+
18
+![](2024-10-09-17-15-09.png)
19
+
20
+
21
+
22
+### sort network classes network
23
+
24
+- schematic setup -> net classes
25
+
26
+
27
+
28
+
29
+### assign the footprints
30
+
31
+![](2024-09-18-01-41-13.png)
32
+
33
+- add symbols and assign footprint
34
+ - enter "E" for properties, and assign the footprint
35
+
PCB-dat/PCB-dat/EDA-dat/kicad-dat/kidcad-workflow-dat/kicad-workflow-dat.md
... ...
@@ -0,0 +1,15 @@
1
+
2
+# kicad work flow
3
+
4
+- prerequisite shortcuts - https://docs.kicad.org/7.0/en/kicad/kicad.html
5
+
6
+
7
+- [[kicad-sch-dat]] -> [[kicad-pcb-dat]]
8
+
9
+
10
+
11
+## ref
12
+
13
+- [[PCB-fab-dat]]
14
+
15
+- [[kicad-workflow]] - [[kicad]]
... ...
\ No newline at end of file
PCB-dat/PCB-dat/EDA-dat/lceda-dat/lceda-dat.md
... ...
@@ -0,0 +1,21 @@
1
+
2
+# easyeda.com-dat
3
+
4
+
5
+
6
+- easyeda.com is a web-based EDA tool that allows users to design and simulate electronic circuits and PCBs. It provides a user-friendly interface and a wide range of features for both beginners and experienced designers.
7
+
8
+- lceda.com
9
+
10
+- pro.easyeda.com
11
+
12
+- support import [[altium-design-dat]] file .pcbdoc
13
+
14
+- support output [[gerber-dat]] file
15
+
16
+
17
+
18
+
19
+## ref
20
+
21
+- [[EDA-dat]]
PCB-dat/PCB-dat/EDA-dat/protel-dat/protel-dat.md
... ...
@@ -0,0 +1,13 @@
1
+
2
+# protel-dat
3
+
4
+- SCH
5
+- PCB
6
+- DDB
7
+
8
+
9
+
10
+
11
+## ref
12
+
13
+- [[protel]]
... ...
\ No newline at end of file
PCB-dat/PCB-dat/EDA-simulation-dat/EDA-simulation-dat.md
... ...
@@ -0,0 +1,49 @@
1
+
2
+# EDA-simulation-dat
3
+
4
+## software
5
+
6
+| Software | Features & Use Case | Free Version Available? |
7
+| ---------------------- | ---------------------------------------------------------------- | ------------------------------- |
8
+| **LTspice** | Powerful SPICE simulator for analog circuits (by Analog Devices) | āœ… Free |
9
+| **KiCad** | Open-source PCB design and SPICE simulation | āœ… Free |
10
+| **Altium Designer** | Industry-standard PCB design and simulation | āŒ Paid (Trial available) |
11
+| **Proteus** | Combines schematic capture, PCB design, and simulation | āŒ Paid (Demo available) |
12
+| **EasyEDA** | Online-based PCB design and simulation | āœ… Free |
13
+| **Multisim** | Advanced SPICE simulation with real-time analysis | āŒ Paid (Free for students) |
14
+| **OrCAD PSpice** | High-end analog and mixed-signal simulation | āŒ Paid (Lite version available) |
15
+| **Fusion 360 (Eagle)** | PCB design with simulation tools (by Autodesk) | āœ… Free for hobbyists |
16
+
17
+- [[kicad-simulation-dat]] - [[eagle-simulation-dat]]
18
+
19
+
20
+## ngspice
21
+
22
+- [manual](https://ngspice.sourceforge.io/docs/ngspice-manual.pdf)
23
+
24
+
25
+https://ngspice.sourceforge.io/ngspice-eeschema.html#BipAmp
26
+
27
+
28
+## PSpice
29
+
30
+- PSpice (OrCAD Capture).
31
+- LTspice
32
+
33
+
34
+- [[LM358-dat]]
35
+
36
+
37
+## online simulation
38
+
39
+https://www.circuitlab.com/editor/#?id=7pq5wm&from=homepage
40
+
41
+support: [[amplifier-dat]], [[NE555-dat]], [[comparator-dat]], [[logic-gate-dat]], ...
42
+
43
+
44
+- [[circuit-lab-dat]]
45
+
46
+## ref
47
+
48
+
49
+- [[EDA-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-dat/EDA-simulation-dat/circuit-lab-dat/circuit-lab-dat.md
... ...
@@ -0,0 +1,12 @@
1
+
2
+# circuit-lab-dat
3
+
4
+- [[amplifier-dat]]
5
+
6
+- [Low Pass Active Filter](https://www.circuitlab.com/editor/#?id=z84zq5)
7
+
8
+
9
+
10
+## ref
11
+
12
+- [[EDA-simulation-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-dat/PCB-accesories-dat/PCB-accesories-dat.md
... ...
@@ -0,0 +1,25 @@
1
+
2
+# PCB-accesories-dat
3
+
4
+- [[heatsink-dat]]
5
+
6
+- [[magnetic-screw-dat]]
7
+
8
+- PCB stand == [[PMP1036-dat]] - [[PMP1037-dat]]
9
+
10
+- hexgon spacer == [[PMP1033-dat]] == https://www.electrodragon.com/product/common-used-m3-hexgon-spacing-bar-screw-kit/
11
+
12
+- [[PMP1016-dat]] - [[PMP1019-dat]] - [[PMP1021-dat]] == https://www.electrodragon.com/product/m3-brazz-bolt-different-length-available/
13
+
14
+- PCB electric isolation
15
+
16
+- äø‰é˜²ę¼† == Conformal Coating
17
+
18
+
19
+
20
+
21
+
22
+
23
+## ref
24
+
25
+- [[PCB-dat]] - [[rover-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-dat/PCB-accesories-dat/magnetic-screw-dat/2024-02-17-14-20-10.png
... ...
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PCB-dat/PCB-dat/PCB-accesories-dat/magnetic-screw-dat/2024-02-17-14-27-40.png
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PCB-dat/PCB-dat/PCB-accesories-dat/magnetic-screw-dat/2024-02-17-14-28-07.png
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PCB-dat/PCB-dat/PCB-accesories-dat/magnetic-screw-dat/magnetic-screw-dat.md
... ...
@@ -0,0 +1,26 @@
1
+
2
+# magnetic-screw-dat
3
+
4
+![](2024-02-17-14-20-10.png)
5
+
6
+## 1317-M3
7
+- diameter 13mm, height 17mm
8
+- drill - M3
9
+
10
+![](2024-02-17-14-27-40.png)
11
+
12
+## 1313-M4
13
+
14
+![](2024-02-17-14-28-07.png)
15
+
16
+
17
+
18
+## Demo video
19
+
20
+https://www.youtube.com/shorts/bYAMpQTe3k0
21
+
22
+
23
+
24
+## ref
25
+
26
+- [[PCB-accesories-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-dat/PCB-dat.md
... ...
@@ -0,0 +1,42 @@
1
+
2
+# PCB-dat
3
+
4
+- [[PCB-design-dat]] - [[PCB-make-dat]]
5
+
6
+
7
+## editing
8
+
9
+- [[tools-PCB-dat]] - [[soldering-dat]]
10
+
11
+- [[desoldering-dat]]
12
+
13
+
14
+
15
+## fab
16
+
17
+- [[fab-dat]]
18
+
19
+- [[fab-PCB-dat]] - [[PCB-format-dat]] - [[PCB-output-common-error-dat]] - [[PCB-penalization-dat]]
20
+
21
+- [[fab-PCBA-dat]]
22
+
23
+- [[fab-stencil-dat]]
24
+
25
+
26
+
27
+## desgin
28
+
29
+- [[4-layer-dat]] - [[0402-dat]]
30
+
31
+- [[PCB-form-dat]]
32
+
33
+- [[BTB-dat]]
34
+
35
+## ref
36
+
37
+- [[PCB-dat]] - [[PCB-layout-dat]]
38
+
39
+
40
+
41
+
42
+
PCB-dat/PCB-dat/PCB-design-dat/2025-08-28-16-29-41.png
... ...
Binary files /dev/null and b/PCB-dat/PCB-dat/PCB-design-dat/2025-08-28-16-29-41.png differ
PCB-dat/PCB-dat/PCB-design-dat/PCB-design-dat.md
... ...
@@ -0,0 +1,50 @@
1
+
2
+# PCB-design-dat
3
+
4
+## design
5
+
6
+- [[footprint-dat]] - [[thermal-disppation-dat]] - [[heatsink-dat]] - [[PCB-installation-dat]]
7
+
8
+
9
+- [[EDA-dat]] - [[EDA-simulation-dat]]
10
+
11
+- [[test-point-dat]]
12
+
13
+
14
+## special
15
+
16
+- [[flex-PCB-dat]]
17
+
18
+## basic
19
+
20
+### PCB layers
21
+
22
+| design layers | funcs |
23
+| ------------- | -------------------------------- |
24
+| tStop | solder mask stop on top layer |
25
+| bStop | solder mask stop on bottom layer |
26
+
27
+- [[EDA-dat]] - [[fab-pcb-dat]] - [[fab-pcba-dat]]
28
+
29
+## ERC Rules
30
+
31
+| mil | mm |
32
+| --- | ------ |
33
+| 6 | 0.1524 |
34
+| 8 | 0.2032 |
35
+| 10 | 0.254 |
36
+| 12 | 0.3048 |
37
+| 16 | 0.4064 |
38
+
39
+
40
+## experiences
41
+
42
+ground protected crystals for [[RP2040-dat]] - [[RPI-dat]]
43
+
44
+![](2025-08-28-16-29-41.png)
45
+
46
+
47
+
48
+## ref
49
+
50
+- [[PCB-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-dat/PCB-design-dat/PCB-installation-dat/PCB-installation-dat.md
... ...
@@ -0,0 +1,8 @@
1
+
2
+# PCB-installation-dat
3
+
4
+- [[hexgon-spacing-dat]]
5
+
6
+## magnetic snapping
7
+
8
+- [[PMP1037-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-dat/PCB-design-dat/PCB-layout-dat/2024-11-13-19-18-09.png
... ...
Binary files /dev/null and b/PCB-dat/PCB-dat/PCB-design-dat/PCB-layout-dat/2024-11-13-19-18-09.png differ
PCB-dat/PCB-dat/PCB-design-dat/PCB-layout-dat/2024-11-13-19-18-21.png
... ...
Binary files /dev/null and b/PCB-dat/PCB-dat/PCB-design-dat/PCB-layout-dat/2024-11-13-19-18-21.png differ
PCB-dat/PCB-dat/PCB-design-dat/PCB-layout-dat/PCB-layout-dat.md
... ...
@@ -0,0 +1,13 @@
1
+
2
+# PCB-layout-dat
3
+
4
+## vertical or 45-degree connectors
5
+
6
+![](2024-11-13-19-18-09.png)
7
+
8
+![](2024-11-13-19-18-21.png)
9
+
10
+
11
+## ref
12
+
13
+- [[PCB-dat]] - [[PCB-layout-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-dat/PCB-design-dat/footprint-dat/SOP8-150-dat/SOP8-150-dat.md
... ...
@@ -0,0 +1,4 @@
1
+
2
+# SOP8-150-dat
3
+
4
+- - width = 3.81 mm = 150 mil
... ...
\ No newline at end of file
PCB-dat/PCB-dat/PCB-design-dat/footprint-dat/SOP8-200-dat/2024-08-29-01-56-56.png
... ...
Binary files /dev/null and b/PCB-dat/PCB-dat/PCB-design-dat/footprint-dat/SOP8-200-dat/2024-08-29-01-56-56.png differ
PCB-dat/PCB-dat/PCB-design-dat/footprint-dat/SOP8-200-dat/SOP8-200-dat.md
... ...
@@ -0,0 +1,6 @@
1
+
2
+# SOP8-200-dat.md
3
+
4
+- width = 5.08 mm
5
+
6
+![](2024-08-29-01-56-56.png)
... ...
\ No newline at end of file
PCB-dat/PCB-dat/PCB-design-dat/test-point-dat/test-point-dat.md
... ...
@@ -0,0 +1,31 @@
1
+
2
+# test-point-dat
3
+
4
+- small batch production can use multimeter to do the test
5
+
6
+add points like
7
+
8
+for power supply - [[power-dat]]
9
+
10
+- VBUS
11
+- 3V3
12
+- GND
13
+
14
+[[epaper-dat]]
15
+
16
+- GDR
17
+- RESET
18
+- VCOM
19
+- PREVGL
20
+- PREVGH
21
+
22
+
23
+- VCOM: Usually between -2V and -3V (sometimes adjustable, check your moduleā€™s datasheet).
24
+- PREVGL: Negative voltage, often around -15V to -20V.
25
+- PREVGH: Positive voltage, often around +15V to +20V.
26
+
27
+VOM
28
+
29
+PRE-VGL == -20V
30
+
31
+PRE-VGH == 20V
... ...
\ No newline at end of file
PCB-dat/PCB-dat/PCB-design-dat/thermal-disppation-dat/thermal-disppation-dat.md
... ...
@@ -0,0 +1,44 @@
1
+
2
+# thermal-disppation-dat
3
+
4
+- [[heatsink-dat]]
5
+
6
+## āš™ļø Key Factors
7
+
8
+The current-carrying capacity of a 2.54mm (0.1 inch) wide PCB trace depends on:
9
+
10
+- **Copper thickness** (measured in oz/ftĀ²)
11
+- **Temperature rise allowed**
12
+- **Trace location** (internal vs. external)
13
+
14
+---
15
+
16
+## šŸ“Š General Guidelines (Based on IPC-2221)
17
+
18
+| Copper Thickness | Trace Type | Temp Rise | Approx. Max Current |
19
+|------------------|----------------|-----------|----------------------|
20
+| 1 oz (35Āµm) | External trace | 10Ā°C | ~2.6 A |
21
+| 1 oz (35Āµm) | External trace | 20Ā°C | ~3.8 A |
22
+| 2 oz (70Āµm) | External trace | 20Ā°C | ~5.0ā€“6.0 A |
23
+| 1 oz (35Āµm) | Internal trace | 20Ā°C | ~2.0ā€“2.5 A |
24
+
25
+> šŸ“ Rule of thumb: For **1 oz copper**, every **1mm width** can safely carry **~1 A** (for external traces and ~10ā€“20Ā°C temp rise).
26
+
27
+---
28
+
29
+## šŸ§  Tips
30
+
31
+- Use **wider traces or thicker copper** if higher current is needed.
32
+- Consider **thermal relief**, **via stitching**, or **multiple layers** for better performance.
33
+- For high currents (>5 A), use **solid copper pours** or **bus bars**.
34
+
35
+---
36
+
37
+## šŸ› ļø Example
38
+
39
+For a **2.54mm wide**, **1 oz copper** external trace with **20Ā°C rise**:
40
+- Safe current = ~3.5ā€“4.0 A
41
+
42
+## ref
43
+
44
+- [[PCB-design-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-dat/PCB-form-dat/PCB-form-dat.md
... ...
@@ -0,0 +1,8 @@
1
+
2
+# PCB-form-dat
3
+
4
+- [[mini-PCIE-dat]]
5
+
6
+## ref
7
+
8
+- [[PCB-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-dat/PCB-tools-dat/2025-05-16-14-18-42.png
... ...
Binary files /dev/null and b/PCB-dat/PCB-dat/PCB-tools-dat/2025-05-16-14-18-42.png differ
PCB-dat/PCB-dat/PCB-tools-dat/PCB-cleaner-dat/PCB-cleaner-dat.md
... ...
@@ -0,0 +1,60 @@
1
+
2
+# PCB-cleaner-dat
3
+
4
+## PCB-cleaner-dat
5
+
6
+### Product Usage Instructions
7
+
8
+Product dimensions and specifications
9
+
10
+**Ultrasonic Cleaning:** Pour the board cleaner into the ultrasonic cleaner, place the PCB board or workpiece to be cleaned inside, turn on the machine, and clean for 4-6 minutes. Then, ventilate and dry for 5-10 minutes.
11
+
12
+**Immersion Cleaning:** Pour this product into a container, immerse the PCB board, then use a brush to scrub it clean, and finally air dry.
13
+
14
+**Spot Cleaning:** Wet a brush or lint-free cloth with this product and directly scrub the oily area. Repeat the scrubbing several times, then air dry.
15
+
16
+**Brush Cleaning:** Pour out this product, soak a brush or lint-free cloth, and then wipe the item that needs cleaning.
17
+
18
+
19
+## Recommended Eco-Friendly and Cost-Effective PCB Cleaner
20
+
21
+### āœ… Recommended Product: Isopropyl Alcohol (IPA, concentration ā‰„ 99%)
22
+
23
+#### šŸ”¹ Features
24
+
25
+- **Eco-Friendly:** Evaporates cleanly with no residue; biodegradable
26
+- **Low Toxicity:** Safer than strong solvents like acetone or trichloroethylene
27
+- **Effective Cleaning:** Removes flux, grease, dust effectively
28
+- **Affordable:** Inexpensive and widely available
29
+- **Versatile:** Suitable for most PCBs and electronic components
30
+
31
+#### šŸ”¹ Precautions
32
+
33
+- Flammable ā€“ keep away from open flames
34
+- Ensure good ventilation during use
35
+- Choose ā‰„99% anhydrous IPA (electronic grade)
36
+
37
+---
38
+
39
+### šŸ†š Common PCB Cleaner Comparison Table
40
+
41
+| Product Name | Eco-Friendliness | Price | Cleaning Power | Conductive | Notes |
42
+|-----------------------|------------------|-----------|----------------|------------|-----------------------------------------|
43
+| Isopropyl Alcohol (IPA) | ā˜…ā˜…ā˜…ā˜…ā˜† | ā˜…ā˜…ā˜…ā˜…ā˜… | ā˜…ā˜…ā˜…ā˜…ā˜† | No | Best value, widely applicable |
44
+| Water-Based Cleaner | ā˜…ā˜…ā˜…ā˜…ā˜… | ā˜…ā˜…ā˜…ā˜…ā˜† | ā˜…ā˜…ā˜…ā˜…ā˜† | No | Safe for equipment, slightly weaker |
45
+| Acetone | ā˜…ā˜…ā˜†ā˜†ā˜† | ā˜…ā˜…ā˜…ā˜…ā˜† | ā˜…ā˜…ā˜…ā˜…ā˜… | No | Strong but harsh, can damage plastics |
46
+| Trichloroethylene | ā˜…ā˜†ā˜†ā˜†ā˜† | ā˜…ā˜…ā˜…ā˜†ā˜† | ā˜…ā˜…ā˜…ā˜…ā˜… | No | Toxic, environmentally restricted |
47
+
48
+---
49
+
50
+### āœ… Summary Recommendation
51
+
52
+> If youā€™re looking for **eco-friendly + affordable + convenient**, the best option is:
53
+>
54
+> ### šŸ‘‰ High-Purity Isopropyl Alcohol (99% IPA)
55
+> Available in bulk or spray form; can be diluted slightly if needed.
56
+
57
+
58
+## ref
59
+
60
+- [[PCB-cleaner]]
... ...
\ No newline at end of file
PCB-dat/PCB-dat/PCB-tools-dat/PCB-tools-dat.md
... ...
@@ -0,0 +1,36 @@
1
+
2
+# tools-PCB-dat
3
+
4
+## modification tools
5
+
6
+- cutting tools == [[PSO1060-dat]], shortly cutt the PCB trace
7
+
8
+- mini drill bits == [[PTO1036-dat]], drill little holes to disconnect the PCB trace
9
+
10
+![](2025-05-16-14-18-42.png)
11
+
12
+
13
+## wires
14
+
15
+- [[flywire-dat]] - [[jumper-wire-dat]] - [[cable-dat]] - [[awg-wires-dat]]
16
+
17
+
18
+
19
+
20
+## other tools
21
+
22
+- [[hot-gun-glue-dat]] - [[glue-dat]]
23
+
24
+## cleaner
25
+
26
+- [[PCB-cleaner-dat]]
27
+
28
+
29
+## soldering rack
30
+
31
+[Soldering Iron Wires Rack w/cleaning slots R2](https://www.electrodragon.com/product/casting-metal-soldering-rack/) - [[PSOS010-dat]]
32
+
33
+
34
+## ref
35
+
36
+- [[tools-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-format-dat/2024-07-31-17-27-05.png
... ...
Binary files /dev/null and b/PCB-dat/PCB-format-dat/2024-07-31-17-27-05.png differ
PCB-dat/PCB-format-dat/PCB-format-dat.md
... ...
@@ -0,0 +1,11 @@
1
+
2
+# PCB-format-dat
3
+
4
+## Common gerber files for (in a .zip)
5
+
6
+![](2024-07-31-17-27-05.png)
7
+
8
+
9
+
10
+
11
+- [[PCB-format]]
... ...
\ No newline at end of file
PCB-dat/PCB-output-common-error-dat/35-10-14-18-07-2023.png
... ...
Binary files /dev/null and b/PCB-dat/PCB-output-common-error-dat/35-10-14-18-07-2023.png differ
PCB-dat/PCB-output-common-error-dat/PCB-output-common-error-dat.md
... ...
@@ -0,0 +1,11 @@
1
+
2
+# PCB common error dat
3
+
4
+- [[PCB-format-dat]]
5
+
6
+
7
+### missing layer for production: no stop mask
8
+
9
+![](35-10-14-18-07-2023.png)
10
+
11
+
PCB-dat/PCB-penalization-dat/56-08-14-18-07-2023.png
... ...
Binary files /dev/null and b/PCB-dat/PCB-penalization-dat/56-08-14-18-07-2023.png differ
PCB-dat/PCB-penalization-dat/PCB-penalization-dat.md
... ...
@@ -0,0 +1,35 @@
1
+# Penalization
2
+
3
+
4
+
5
+## methods
6
+
7
+
8
+
9
+#### Castellated holes
10
+
11
+Castellated holes, please make sure your board are designed correctly: Place holes, add V-cuts, etc
12
+
13
+![](56-08-14-18-07-2023.png)
14
+
15
+
16
+
17
+# penalization-dat
18
+
19
+- [[many-penalization-examples-dat]]
20
+
21
+
22
+## ref
23
+
24
+- [[stamp-holes-dat]]
25
+
26
+- [[ę‹¼ęæ]]
27
+
28
+
29
+
30
+
31
+
32
+## obseleted
33
+
34
+* [http://dl.electrodragon.com/k/index.php?share/file&user=1&sid=wsIZnGKW 1. Eagle penalize and export gerber file]
35
+* [http://dl.electrodragon.com/k/index.php?share/file&user=1&sid=eKTRh7b3 2. detailed panelized tutorial]
PCB-dat/PCB-penalization-dat/many-penalization-examples-dat/2025-05-16-16-55-09.png
... ...
Binary files /dev/null and b/PCB-dat/PCB-penalization-dat/many-penalization-examples-dat/2025-05-16-16-55-09.png differ
PCB-dat/PCB-penalization-dat/many-penalization-examples-dat/2025-05-16-16-55-21.png
... ...
Binary files /dev/null and b/PCB-dat/PCB-penalization-dat/many-penalization-examples-dat/2025-05-16-16-55-21.png differ
PCB-dat/PCB-penalization-dat/many-penalization-examples-dat/2025-05-16-16-55-31.png
... ...
Binary files /dev/null and b/PCB-dat/PCB-penalization-dat/many-penalization-examples-dat/2025-05-16-16-55-31.png differ
PCB-dat/PCB-penalization-dat/many-penalization-examples-dat/2025-05-16-16-55-39.png
... ...
Binary files /dev/null and b/PCB-dat/PCB-penalization-dat/many-penalization-examples-dat/2025-05-16-16-55-39.png differ
PCB-dat/PCB-penalization-dat/many-penalization-examples-dat/2025-05-16-16-56-27.png
... ...
Binary files /dev/null and b/PCB-dat/PCB-penalization-dat/many-penalization-examples-dat/2025-05-16-16-56-27.png differ
PCB-dat/PCB-penalization-dat/many-penalization-examples-dat/many-penalization-examples-dat.md
... ...
@@ -0,0 +1,27 @@
1
+
2
+# many-penalization-examples-dat
3
+
4
+## eg1. - [[OPM1175-dat]]
5
+
6
+- [[OPM1175-dat]]
7
+
8
+![](2025-05-16-16-55-09.png)
9
+
10
+![](2025-05-16-16-55-21.png)
11
+
12
+![](2025-05-16-16-55-31.png)
13
+
14
+![](2025-05-16-16-55-39.png)
15
+
16
+PCB Grooving gap = 1mm, drill hole == 0.3mm
17
+
18
+![](2025-05-16-16-56-27.png)
19
+
20
+
21
+## eg2. -
22
+
23
+
24
+
25
+## ref
26
+
27
+- [[fab-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-standards-dat/PCB-standards-dat.md
... ...
@@ -0,0 +1,95 @@
1
+
2
+# PCB-standards-dat
3
+
4
+- 8 mil = 0.2 mm
5
+- 10 mil = 0.25 mm (common used)
6
+- 12 mil = 0.3048 mm
7
+- 14 mil = 0.3556 mm
8
+
9
+| category | Standards | 0.2 mm | 10 mil | Note. CN |
10
+| --------- | ---------------------- | -------------- | ------ | -------- |
11
+| clearance | Wire -> Wire, Pad, Via | 0.2 mm | | |
12
+| clearance | Wire -> edge | 0.2 mm | | |
13
+| Size | Signal Width | 0.2 mm | | |
14
+| Size | Minimum Drill | 0.25 mm | | |
15
+| Miscs. | roundness | 0.15 mm @ 100% | | |
16
+| Miscs. | Mask | 0.1mm @ 100% | | |
17
+| Misc. | Min. Diameter | | | |
18
+| Misc. | Annular Ring | | | |
19
+
20
+
21
+
22
+
23
+
24
+### Other Manufacturing Limits
25
+
26
+| Type | Specs | Note |
27
+| -------------------------------- | -------------------------------------- | ------------------------------------ |
28
+| PCB Type | FR-4 from KB company | - |
29
+| Maximum size | 1200mm X1200mm | more than 550mm prices will increase |
30
+| Dimensions accuracy of board | Ā± 0.2mm | - |
31
+| Thickness range | 0.40~3mm | - |
32
+| Thickness tolerance | Ā±10% | - |
33
+| Dielectric thickness | 0.075 - 5.00mm | - |
34
+| Copper thickness | 17um - 100um | default 1OZ 35um, 0.035mm |
35
+| Drilling Hole | 0.3mm - 6.30mm | - |
36
+| Drilling Hole Tolerances | 0.08mm | - |
37
+| Drilling Hole position tolerance | 0.09mm | - |
38
+| Pour hypotenuse | 30~60 Ā° | - |
39
+| Color | red, blue, green, white, yellow, black | default green\|- |
40
+| Soldering Pads Plating | HASL, ROSH (lead-free), ENIG | |
41
+
42
+
43
+
44
+
45
+
46
+
47
+## Manufacturing capability
48
+Please adapte this to your own "DRC(Design Rule Check)" tool, to make sure your board reach the manufacturing limits.<br />
49
+
50
+### Common-Used Design Ruled DRC
51
+
52
+| Name | Min. inch (mm) | Max. | Eagle CAD Default |
53
+| ----------------------------------- | ------------------- | ------------------ | ----------------- |
54
+| Trace Width/Spacing | 6/6 mils (0.15 mm) | - | 10/8 mils |
55
+| Via/Hole Spacing | 6 mils (0.15 mm) | - | 8 mils |
56
+| Drilling hole (vias) | 10 mils (0.25 mm) * | 250 mils (6.35 mm) | Sizes 24 mils |
57
+| Min. stop mask | 4 mils (0.1 mm) | - | Masks 4 mils |
58
+| Min. copper/trace to ground spacing | 8 mils (0.2 mm) | - | 40 mils |
59
+
60
+
61
+### Note
62
+* Minimum milling width of grooves is 0.8mm
63
+* A lot numbers of vias may cost extra
64
+* Dimension: Any irregular shape should be treated as a rectangular, with maximum size.
65
+* Board test:Ā  fully tested by fly probes.
66
+
67
+#### Half-Hole/Impedance
68
+- Half-Hole + $20, if you need this please contact first or write note in order.
69
+- Impedance + $60
70
+
71
+### What do not support
72
+* Four layers boards
73
+* Blind holes (not through holes).
74
+
75
+
76
+
77
+
78
+### Extra PCB Technics
79
+
80
+| Type | Description | Category |
81
+| ---------------------- | ------------------------------------------------------------------------------------------------------------------------------------------- | ---------------------------- |
82
+| Lead free ROHS | free for samples, extra cost for batch production | Soldering Pads Plate Technic |
83
+| ENIG | Gold immersion on pads, better look, better soldering, etc | Soldering Pads Plate Technic |
84
+| Faster PCB in 30 Hours | PCB Manufacturing will be finished in one and half day, not including shipping and handing time. Cost is 42 USD. Can not with ENIG service. | Express PCB |
85
+| Faster PCB in 53 Hours | PCB Manufacturing will be finished in two and half day, not including shipping and handing time. Cost is 21 USD. | Express PCB |
86
+| 2oz copper thickness | Get better heat dissipation for your board, example like A4988 board. | - |
87
+| Board thickness | Free from 0.6 till 1.6 mm, extra cost need for 0.4 and 2.0 mm thickness. (available thickness 0.4 0.6 0.8 1.0 1.2 1.6 2.0) | - |
88
+
89
+
90
+
91
+
92
+
93
+## ref
94
+
95
+- [[kicad-dat]]
... ...
\ No newline at end of file
PCB-dat/fab-PCB-dat.md
... ...
@@ -0,0 +1,87 @@
1
+
2
+# fab-PCB-dat
3
+
4
+
5
+- legacy wiki page - https://w.electrodragon.com/w/Category:PCB
6
+
7
+## PCB production design
8
+
9
+- [[PCB-penalization-dat]]
10
+
11
+## output PCB file
12
+
13
+- [[PCB-output-common-error-dat]]
14
+
15
+- to understand the manufacturing capability, see here - [[PCB-standards-dat]]
16
+
17
+- check correct output format - [[PCB-format-dat]]
18
+
19
+
20
+
21
+### Order self-Check List
22
+
23
+- layer: 1, 2, 4, 6, 8
24
+- Output Type: Single, Continious(As file), Countinious (By our engineer)
25
+- Size: ? x ? mm
26
+- Quantity: ? pcs
27
+- Technic Edge (If single, or penalized by us) : ? mm, up/bottom, left/right, all, none
28
+- Penalize Rules (If penalized by us): ? x ? pcs
29
+- Thickness: 0.6, 0.8, 1.0, 1.2, 1.6, 2.0 (+100), 2.5 (N/A now)
30
+- Copper Thickness: 1oz, 2oz
31
+- Min. Trace Width/Spacing: 6/6 mil, 5/5 mil (+15), 4/4 mil (+65), 3/3 mil (N/A now)
32
+- Min. Drill: 0.3 mm, 0.25 mm (+30), 0.2 mm (+30),
33
+- Stop Mask Color: Green, Blue, Red, Yellow, Black, Near-Black, White
34
+- Character Color: White, Black
35
+- Stop-mask Cover: Vias covered, Vias not covered, If gerber files defined then follow gerber!
36
+- Solder Pads Plate: Lead, Lead Free (+30), Gold Plated (+100)
37
+- Test Numbers: 0,
38
+- Test Method: Sample Free,
39
+- Half-hole: None Default, Yes
40
+- Impedence: None Default, Yes
41
+
42
+
43
+
44
+
45
+### FAQ
46
+
47
+##### Stop Mask on the Vias?
48
+Yes, stop mask will cover the vias, but not the pads, please be aware on this point.
49
+
50
+##### What is dimension requirement of Drilling?
51
+- Drilling as not padding diameter range from 0.3 mm to infinity
52
+- Drilling as pads diameter range from 0.3 mm to 6mm
53
+- Drill shape doesn't not support rectangular, most of other shape are no problem.
54
+-
55
+##### What is the price for different board thickness?
56
+For 0.8 - 1.6 mm thickness board, the price is default, without this arrange there will be an extra charge.
57
+
58
+##### What is the price for board over size 10*10 CM
59
+Please contact us to get a quote.
60
+
61
+##### What is lead time of this service
62
+For 5*5 cm and 10*10 cm sample PCBs, the lead time is 4-6 days that not including Sunday. For more than 50pcs 10*10 cm batch or similar to that, we will have 2-3 days extra for production.
63
+
64
+
65
+
66
+
67
+== PCB Production Cost List ==
68
+
69
+## quantity setup
70
+
71
+The quantity must be a multiple of 5.
72
+
73
+| PCB quantity | penalization (e.g.) | total |
74
+| ------------ | ------------------- | ----- |
75
+| 5 | 8 | 40 |
76
+| 10 | 8 | 80 |
77
+| 15 | 8 | 120 |
78
+| 20 | 8 | 160 |
79
+| 25 | 8 | 200 |
80
+| 30 | 8 | 240 |
81
+
82
+
83
+## ref
84
+
85
+- [[PCBA-dat]]
86
+
87
+- [[fab-PCB-dat]]
fab-PCB-dat/PCB-dat/4-layer-dat/4-layer-dat.md
... ...
@@ -1,71 +0,0 @@
1
-
2
-# 4-layer-dat
3
-
4
-## specs
5
-
6
-- inner layer == 0.5 oz
7
-
8
-
9
-## lamination
10
-
11
-The typical lamination order for a 4-layer PCB is:
12
-
13
-- Top Layer: Signal layer
14
-- Inner Layer 1: Power plane (e.g., VCC or GND)
15
-- Inner Layer 2: Ground plane (e.g., GND or VCC)
16
-- Bottom Layer: Signal layer
17
-
18
-### lamination order
19
-
20
-"4-layer PCB stack-up:
21
-
22
-- Top Layer: Signal
23
-- Inner Layer 1: Power (VCC)
24
-- Inner Layer 2: Ground (GND)
25
-- Bottom Layer: Signal
26
-
27
-Please follow this lamination order for manufacturing."
28
-
29
-### šŸ”„ Typical 4-Layer Stackup (Example)
30
-
31
-| Layer | Purpose |
32
-|-------|-----------------------------|
33
-| L1 | Signal (High-speed / Logic) |
34
-| L2 | Ground Plane |
35
-| L3 | Power Plane (3.3V, etc.) |
36
-| L4 | Signal (Slower or routing) |
37
-
38
-This stackup helps with:
39
-- Good **signal integrity** (especially PCIe or USB lines)
40
-- **Controlled impedance** for high-speed routing
41
-- **Noise reduction** and **EMI compliance**
42
-
43
----
44
-
45
-## āš™ļø Why Use 4 Layers?
46
-
47
-| Reason | Explanation |
48
-|-------------------------------|---------------------------------------------|
49
-| Signal integrity | PCIe and USB need impedance control |
50
-| Power distribution | Separate plane ensures clean power |
51
-| Ground return path | Reduces EMI / crosstalk |
52
-| Compact routing | Easier routing in tight Mini PCIe space |
53
-
54
----
55
-
56
-## šŸ”§ Considerations
57
-
58
-- Use **controlled impedance** (50Ī© for USB, 85Ī© diff for PCIe)
59
-- Ensure **gold fingers** are ENIG plated and follow **Mini PCIe spec**
60
-- Route high-speed signals on **L1 and L4**, with ground under them
61
-- Place components only on the **top layer**, per Mini PCIe mechanical spec
62
-- Follow PCI-SIG or Mini PCIe spec for **connector layout** and **keep-outs**
63
-
64
-
65
-## ref
66
-
67
-- [[PCB-dat]]
68
-
69
-- [[camera-dat]]
70
-
71
-- [[c]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/EDA-dat/EDA-dat.md
... ...
@@ -1,20 +0,0 @@
1
-
2
-# EDA-dat.md
3
-
4
-- [[eaglecad-dat]]
5
-
6
-- [[kicad-dat]]
7
-
8
-- [[LCEDA]]
9
-
10
-- [[altium-designer-dat]]
11
-
12
-- [[protel-dat]]
13
-
14
-
15
-
16
-
17
-
18
-## ref
19
-
20
-- [[PCB-dat]] - [[PCBA-dat]] - [[EDA-dat]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/EDA-dat/eaglecad-dat/2024-04-02-14-24-27.png
... ...
Binary files a/fab-PCB-dat/PCB-dat/EDA-dat/eaglecad-dat/2024-04-02-14-24-27.png and /dev/null differ
fab-PCB-dat/PCB-dat/EDA-dat/eaglecad-dat/2024-04-02-14-24-54.png
... ...
Binary files a/fab-PCB-dat/PCB-dat/EDA-dat/eaglecad-dat/2024-04-02-14-24-54.png and /dev/null differ
fab-PCB-dat/PCB-dat/EDA-dat/eaglecad-dat/eagle-simulation-dat/eagle-simulation-dat.md
... ...
@@ -1,42 +0,0 @@
1
-
2
-# eagle-simulation-dat
3
-
4
-
5
-## add model card for spice, examples
6
-
7
-D:\EAGLE 9.6.2\examples\spice\examples\OPAMP.mdl
8
-
9
-
10
-
11
-## The model card does not include the required .MODEL line, please check your model.
12
-
13
-The model card cannot include subcircuit definitions.
14
-
15
- * BASIC OP AMP MODEL
16
- * Device Pins In+ In- vdd vss Vout
17
- * vdd vss unused in this model!!
18
- .SUBCKT opamp 1 2 vdd vss vout
19
- *
20
- * INPUT
21
- RIN 1 2 1e9
22
- *
23
- * AMPLIFIER STAGE: GAIN, POLE, SLEW
24
- * Aol=10000, fu=1000000 Hz
25
- G1 0 10 VALUE = { 1e-2 * V(1,2) }
26
- R1 10 0 1e6
27
- C1 10 0 1.59e-9
28
- *
29
- * 2ND POLE
30
- G2 0 20 10 0 1e-6
31
- R2 20 0 1e6
32
- C2 20 0 3.3e-14
33
- *
34
- * 3RD POLE
35
- G3 0 30 20 0 1e-6
36
- R3 30 0 1e6
37
- C3 30 0 3.3e-14
38
- *
39
- * OUTPUT STAGE
40
- EBUFFER 80 0 30 0 1
41
- ROUT 80 vout 100
42
- .ENDS opamp
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/EDA-dat/eaglecad-dat/eaglecad-dat.md
... ...
@@ -1,28 +0,0 @@
1
-
2
-# eagle-CAD-dat
3
-
4
-- https://github.com/Edragon/Eagle-CAD-dat
5
-- ~~https://github.com/Edragon/CAD-Eagle-part~~
6
-
7
-
8
-## Tips
9
-
10
-### oval, or oblong shapes
11
-
12
-Unfortunately there is still no option for creating a plated slot in the library editor with the ease you can an SMD or PAD. However, you can do as @millingm suggested or the variation I prefer which is a PAD on each end of the slot and then draw each of the inner/outer layer pad areas with a polygon on each of the 16 routing layers. The also draw the slot as a line on the Milling layer. You end up with something like this in your library:
13
-
14
-![](2024-04-02-14-24-27.png)
15
-
16
-And when it is in the board you end up with:
17
-
18
-![](2024-04-02-14-24-54.png)
19
-
20
-https://forums.autodesk.com/t5/eagle-forum/slotted-pads/td-p/7487203
21
-
22
-
23
-
24
-
25
-
26
-## ref
27
-
28
-- [[eagle-cad]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/EDA-dat/fritzing.org-dat/fritzing.org-dat.md
... ...
@@ -1,4 +0,0 @@
1
-
2
-# fritzing.org-dat
3
-
4
-https://fritzing.org/
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-dat.md
... ...
@@ -1,48 +0,0 @@
1
-
2
-# kicad-dat
3
-
4
-- lib ꗧē‰ˆ ē¬¦å·ę–‡ä»¶
5
-
6
-- [[kicad-workflow-dat]] - [[kicad-plugin-dat]] - [[kicad-shortcuts-dat]]
7
-
8
-- [[kicad-lib-dat]] - [[kicad-data-dat]] - [[kicad-setup-dat]]
9
-
10
-- [[kicad-symbol-dat]] - [[kicad-footprint-dat]]
11
-
12
-- [[kicad-simulation-dat]]
13
-
14
-
15
-
16
-
17
-## Glossary
18
-
19
-### DCM = documentation file
20
-
21
-If you donā€™t copy the DCM files, you will lose the documentation. I believe that the library will otherwise still function but donā€™t quote me on that; you can try it and find out.
22
-
23
-(maybe goes with out saying, but in v6 you only have a single .kicad_sym file which contains all the info)
24
-
25
-### .mod
26
-** Files that end in ā€œ.kicad_modā€, typically in folders with names that end in ā€œ.prettyā€, are the 2014(?) version of modules (a KiCad ā€œmoduleā€ is called a ā€œfootprintā€ or a ā€œdecalā€ in other CAD software), one footprint per file, lots of files in the entire ā€œ.prettyā€ library.*
27
-
28
-** Files that end in ā€œ.modā€ are module libraries (a KiCad ā€œmoduleā€ is called a ā€œfootprintā€ or a ā€œdecalā€ in other CAD software)*
29
-
30
-
31
-## Tips
32
-
33
-### Renaming all associated netnames
34
-
35
-https://gitlab.com/kicad/code/kicad/-/issues/5151
36
-
37
-TIL that Find/Replace is for more than just text (like any other tool)
38
-
39
-alt ctrl F
40
-
41
-
42
-## Features
43
-
44
-- [[reverse-engineering-dat]]
45
-
46
-## ref
47
-
48
-- [[kicad]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-data-dat.md
... ...
@@ -1,28 +0,0 @@
1
-
2
-# kicad-data-dat.md
3
-
4
-## labels
5
-
6
-https://t.me/electrodragon3/253
7
-
8
-copy mutiple labels from kicad, paste here, and can be copied back once edition done.
9
-
10
-(label "DAI" (at 100.33 392.43 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "0cabd4dc-e713-45de-8364-1815a0e2f378"))
11
-(label "DFC" (at 100.33 420.37 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "148c8dd8-9aee-4311-8806-46c0dfb928be"))
12
-(label "DDC" (at 100.33 410.21 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "17577330-cb40-4248-bedd-2e3030fd3781"))
13
-(label "DEI" (at 100.33 412.75 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "b5aa1c90-3cf0-44b0-85fe-720de64bc716"))
14
-(label "DAC" (at 100.33 394.97 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "b69ab755-8299-436c-9a2b-c757923ef6f8"))
15
-(label "DEC" (at 100.33 415.29 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "a67ffca3-b51e-4bda-b76d-416d5275c15b"))
16
-(label "DCC" (at 100.33 405.13 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "a113b754-b329-46c5-98f9-d549d4fd6091"))
17
-(label "DFI" (at 100.33 417.83 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "55acfa6a-5920-4eca-a678-1d1233d27332"))
18
-(label "DHI" (at 100.33 427.99 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "5534b9d1-6bf9-4427-950f-85a4b775e475"))
19
-(label "DHC" (at 100.33 430.53 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "9784cdd3-6225-40f0-aa0e-383216de333b"))
20
-(label "DDI" (at 100.33 407.67 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "c78290c8-0cf7-4e5b-98af-767101b1ea27"))
21
-(label "DBI" (at 100.33 397.51 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "cf988d22-b3b9-4dba-a82d-ff2d0943401e"))
22
-(label "DGC" (at 100.33 425.45 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "bee3fd6d-1ea9-4468-82e5-83bb127095ec"))
23
-(label "DCI" (at 100.33 402.59 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "d6c63f27-b435-456b-b720-0dadbd0c27b4"))
24
-(label "DBC" (at 100.33 400.05 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "e11f0e4c-b5ae-4f6b-abe2-c4ac16cbf189"))
25
-(label "DGI" (at 100.33 422.91 0) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify left bottom))(uuid "e720d05b-ef4d-4914-a12f-a25d7dfec183"))
26
-
27
-
28
-
fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-lib-dat/2025-04-29-15-16-53.png
... ...
Binary files a/fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-lib-dat/2025-04-29-15-16-53.png and /dev/null differ
fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-lib-dat/kicad-footprint-dat.md
... ...
@@ -1,80 +0,0 @@
1
-
2
-# kicad-footprint-dat.md
3
-
4
-- [[kicad-symbol-dat]] - [[kicad-pcb-dat]]
5
-
6
-## custom build footprint guide
7
-
8
-![](2025-04-29-15-16-53.png)
9
-
10
-## common used global library
11
-
12
-- Connector_pinheader
13
-- Connector_Wire
14
- - SolderingWirePad_1x01_SMD_1x2mm
15
-- Connector_USB
16
- - USB_C_Receptacle_G-Switch_GT-USB-7010ASV
17
- - USB_A_CNCTech_1001-011-01101_Horizontal == [[USB-A-dat]]
18
-- MountingHole
19
- - MountingHole_3.2mm_M3
20
-- Package_SO
21
- - SOIC-8_5.3x5.3mm_P1.27mm
22
- - SOIC-16_10.3x7.5mm_P1.27mm
23
- - SOP-8_3.9x4.9mm_P1.27mm
24
- - SOP-8_3.76x4.96mm_P1.27mm
25
-
26
-
27
-
28
-## other collections
29
-
30
-[Kicad_FPC_board_ends](https://github.com/mikeWShef/Kicad_FPC_board_ends)
31
-
32
-
33
-
34
-## QA
35
-
36
-how to import or open kicad .mod file?
37
-
38
-
39
-`.mod` is KiCadā€™s **legacy footprint library** format (preā€“KiCad 5).
40
-
41
-Modern KiCad uses `.kicad_mod` files inside `.pretty` folders.
42
-
43
-
44
-### Method 1 ā€” Import with Library Wizard (Legacy Loader)
45
-
46
-1. Open **PCB Editor**.
47
-2. Go to **Preferences ā†’ Manage Footprint Libraries**.
48
-3. Click **Append with Wizard** (or **Add existing library**).
49
-4. Select your **`.mod`** file.
50
-5. Finish the wizard ā†’ the legacy library is added and usable.
51
-
52
-
53
-### Method 2 ā€” Convert to Modern `.pretty` Library (Recommended)
54
-
55
-Use KiCadā€™s converter to create a modern library:
56
-
57
-~~kicad-footprint2pretty old_library.mod new_library.pretty~~
58
-
59
-**footprint editor -> import -> select .mod file**
60
-
61
-Result: new_library.pretty/ containing individual *.kicad_mod footprints.
62
-
63
-Then in PCB Editor: Preferences ā†’ Manage Footprint Libraries ā†’ Add the new .pretty path.
64
-
65
-### Method 3 ā€” Use Older KiCad to Re-save
66
-
67
-Open the .mod in KiCad v4 (or compatible).
68
-
69
-Export/Save footprints to a .pretty library, then add it in current KiCad.
70
-
71
-Tips
72
-Keep original .mod as a backup.
73
-
74
-After conversion, verify pad sizes, layers, and 3D model links.
75
-
76
-
77
-
78
-## ref
79
-
80
-- [[kicad-symbol-dat]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-lib-dat/kicad-lib-dat.md
... ...
@@ -1,20 +0,0 @@
1
-
2
-# kicad-lib.md
3
-
4
-
5
-
6
-## common used lib
7
-
8
-- power
9
- - +5V
10
- - GND
11
-- Device
12
- - R == resistor
13
- - LED
14
-
15
-
16
-## simulation
17
-
18
-- simulation_SPICE
19
- - vdc
20
-
fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-lib-dat/kicad-symbol-dat.md
... ...
@@ -1,45 +0,0 @@
1
-
2
-# kicad-symbol-dat.md
3
-
4
-- [[kicad-footprint-dat]]
5
-
6
-## custom build symbol guide
7
-
8
-## common used global symbol A to Z
9
-
10
-- Amplifier_Current
11
-- Amlifier_Operational
12
-- Battery_Management
13
- - TP4056-42-ESOP8 == [[TP4056-dat]]
14
-- Connector
15
- - Conn_01x01_Pin
16
- - USB_C_Plug
17
- - USB_A == type A plugger == [[USB-A-dat]]
18
-- Connector_generic_MountingPin
19
-- Device
20
- - C == [[capacitor-dat]]
21
- - R == [[resistor-dat]]
22
- - LED == [[LED-dat]]
23
-- interface_USB
24
- - CH340N
25
-- Jumper
26
- - SolderingJumper
27
-- Mechanicals
28
- - MountingHole
29
-- MCU_Microchip_ATTiny
30
-- Power
31
- - GND
32
-- RF_Module
33
-- Switch
34
- - SW_DPDP_2x
35
-- Interface_Optical
36
- - SFP+
37
- - SFP
38
-
39
-## ref
40
-
41
-- [[kicad-footprint-dat]]
42
-
43
-- [[USB-dat]]
44
-
45
-
fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-plugin-dat/2024-09-22-03-39-54.png
... ...
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fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-plugin-dat/kicad-plugin-dat.md
... ...
@@ -1,61 +0,0 @@
1
-
2
-# kicad-plugin
3
-
4
-## testing
5
-
6
-- interactive html bom
7
-- pcb-action-tools
8
-- board2pdf
9
-- kikit
10
-- kibuzzard - custom font label generator
11
-- archive 3d models
12
-- aisler push for kicad
13
-- place footprints
14
-- replicate layout
15
-- round tracks
16
-- save/restore layout
17
-- fabrication toolkit
18
-- stretch
19
-- keyboard footprints placer
20
-- kimotor
21
-- pinout generator
22
-- transform it
23
-- oktizer action plugin
24
-- bulk hide silkscreen designators
25
-- impart gui for kicad
26
-- gerber to order
27
-- hide references
28
-- KLEPlacement
29
-- hierarchicalPCB
30
-- sparkfun kicad panelizer
31
-- parasitics
32
-- PCBway fabrication toolkit
33
-- kimesh
34
-- PCB coil generator
35
-- sparkfun kicad CAMer
36
-- kicad coil generator
37
-- Git plugin
38
-- thermal relief via
39
-- pcb2blender
40
-- KiVar
41
-- Swapstubs
42
-- KiCAD testpoints
43
-- cut tracks at line
44
-- HQ PCB
45
-- parts placer
46
-- set hole diameter
47
-- via patterns
48
-- schematic blocks plug-in
49
-
50
-
51
-## useful
52
-
53
-- freerouting - https://hackaday.com/2023/04/14/kicad-autorouting-made-easy/
54
-
55
-![](2024-09-22-03-39-54.png)
56
-
57
-
58
-## install java TLS version
59
-
60
-- https://adoptium.net/download/
61
-
fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-setup-dat.md
... ...
@@ -1,42 +0,0 @@
1
-
2
-# kicad-setup-dat.md
3
-
4
-installation == D:\Program Files\KiCad\9.0\bin
5
-
6
-## preferences
7
-
8
-configure paths
9
-
10
-| Name | Path |
11
-| ----------------------- | -------------------------------------------------- |
12
-| KICAD9_3DMODEL_DIR | D:\Program Files\KiCad\9.0\share\kicad\3dmodels\ |
13
-| KICAD9_3RD_PARTY | D:\HE2\Documents\KiCad\9.0\3rdparty |
14
-| KICAD9_DESIGN_BLOCK_DIR | D:\Program Files\KiCad\9.0\share\kicad\blocks\ |
15
-| KICAD9_FOOTPRINT_DIR | D:\Program Files\KiCad\9.0\share\kicad\footprints\ |
16
-| KICAD9_SYMBOL_DIR | D:\Program Files\KiCad\9.0\share\kicad\symbols\ |
17
-| KICAD9_TEMPLATE _DIR | D:\Program Files\KiCad\9.0\share/kicad/template |
18
-| KICAD_USER_TEMPLATE_DIR | D:\HE2\Documents\KiCad\9.0\template\ |
19
-
20
-
21
-## Available path substitutions:
22
-
23
-| variables | paths |
24
-| -------------------- | ----------------------------------------------- |
25
-| ${KICAD9_SYMBOL_DIR} | D:\Program Files\KiCad\9.0\share\kicad\symbols\ |
26
-| ${KIPRJMOD} | D:\Dropbox\PCB\kicad\proj\USB-HFBR |
27
-
28
-
29
-
30
-
31
-## Common Error
32
-
33
-
34
-### Software Stuck // no respone // freezing
35
-
36
-- This is a IME problem, if you use any other languages input methods, switch back to default ENG
37
-
38
-
39
-## ref
40
-
41
-- [[kicad-dat]]
42
-
fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-shortcuts-dat/kicad-shortcuts-dat.md
... ...
@@ -1,6 +0,0 @@
1
-
2
-# kicad-shortcuts-dat
3
-
4
-A == symbol
5
-
6
-
fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-simulation-dat/2025-03-18-14-46-38.png
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fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-simulation-dat/2025-03-18-15-39-01.png
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fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kicad-simulation-dat/kicad-simulation-dat.md
... ...
@@ -1,107 +0,0 @@
1
-
2
-# kicad-simulation-dat
3
-
4
-- [[LM358-dat]]
5
-
6
-- [[EDA-simulation-dat]]
7
-
8
-## Import SPICE model
9
-
10
-SPICE model from file (*.lib, *.sub or *ibs)
11
-
12
-## custom build
13
-
14
-LED
15
-
16
-I opened their ā€œTools and supportā€ tab, underneath I, found a design resources tab. (figure 1)
17
-
18
-![](2025-03-18-14-49-30.png)
19
-
20
-Underneath design resources they asked for the type of document, I chose ā€œSimulation Modelsā€ (figure 2)
21
-
22
-I searched for the part by name: ā€œBC547ā€. We want the library, so we choose ā€œBC547 Lib Modelā€ and downloaded it. (figure 3)
23
-
24
-
25
-OP-Amp
26
-
27
-![](2025-03-18-15-22-45.png)
28
-
29
-## setup
30
-
31
-[VDC](https://ngspice.sourceforge.io/docs/ngspice-html-manual/manual.xhtml#sec_Independent_Sources_for)
32
-
33
-
34
-### LED
35
-
36
-![](2025-03-18-14-46-38.png)
37
-LEDs are a bit trickier in the fact that modeling them requires some knowledge about their parameters and curve-fitting. So, to model them I just looked up ā€œLED ngspiceā€.
38
-
39
-I found multiple people posting their ā€œLED modelsā€ and I decided to go with this
40
-
41
-ā€œ *Typ RED GaAs LED: Vf=1.7V Vr=4V If=40mA trr=3uS .MODEL LED1 D (IS=93.2P RS=42M N=3.73 BV=4 IBV=10U + CJO=2.97P VJ=.75 M=.333 TT=4.32U)?ā€
42
-
43
-
44
-## download
45
-
46
-
47
-[Simulation examples for KiCad8/KiCad9/Eeschema/ngspice](https://forum.kicad.info/t/simulation-examples-for-kicad8-kicad9-eeschema-ngspice/45546)
48
-
49
-- Generic symbols with generic models, see intro4
50
-- Another 555 circuit example
51
-
52
-[github collections](https://github.com/labtroll/KiCad-Simulations)
53
-
54
-[simulation-examples-for-kicad-eeschema-ngspice](https://forum.kicad.info/t/simulation-examples-for-kicad-eeschema-ngspice/34443/4)
55
-
56
-
57
-## tuto kicad 9
58
-
59
-[ref tutorial](https://ngspice.sourceforge.io/ngspice-eeschema.html#OpAmp)
60
-
61
-
62
-### simple - voltage ladder
63
-
64
-![](2025-03-18-16-04-42.png)
65
-
66
-
67
-### AC Since - RC Ladder
68
-
69
-Schematic Setup
70
-
71
-![](2025-03-18-15-39-01.png)
72
-
73
-SPICE Simulator
74
-
75
-![](2025-03-18-15-35-42.png)
76
-
77
-### Inverting Amplifier - Transient Analysis
78
-
79
-https://www.youtube.com/watch?v=6YvECTfwVOw
80
-
81
-
82
-## tuto
83
-
84
-https://www.instructables.com/Simulating-a-KiCad-Circuit/
85
-
86
-3Y ago
87
-https://www.youtube.com/watch?v=pCQ4MUyQjx0
88
-
89
-https://www.kicad.org/discover/spice/
90
-
91
-simple transistor build and simulate
92
-https://www.woolseyworkshop.com/2019/07/01/performing-a-circuit-simulation-in-kicad/
93
-
94
-
95
-## OPA1641
96
-
97
-- need to fix the pin assignment
98
-- [great tuto here](https://www.youtube.com/watch?v=Wg7uSs4J_0U)
99
-
100
-Transient Analysis == step 10u / final 10m
101
-
102
-![](2025-03-18-18-18-23.png)
103
-
104
-
105
-## ref
106
-
107
-- [[kicad-dat]] - [[voltage-divider-dat]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kidcad-workflow-dat/kicad-pcb-dat/2023-12-11-00-04-17.png
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fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kidcad-workflow-dat/kicad-pcb-dat/95e854b5209f226b023ebe7765500e9.png
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fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kidcad-workflow-dat/kicad-pcb-dat/kicad-pcb-dat.md
... ...
@@ -1,108 +0,0 @@
1
-
2
-# kicad-pcb-dat
3
-
4
-## import from other template projects
5
-
6
-pre-defined file: D:\Program Files\KiCad\8.0\share\kicad\template\Arduino_Nano
7
-
8
-- DRC rules = design rules constrains
9
-- teardrop defaults
10
-
11
-
12
-
13
-![](2024-10-08-19-42-52.png)
14
-
15
-
16
-
17
-### update into PCB
18
-
19
-
20
-
21
-- switch to PCB
22
-- update from PCB
23
-- fix errors
24
-- update PCB
25
-- layout it
26
-
27
-![](2024-09-18-01-43-12.png)
28
-
29
-![](2024-09-18-01-43-55.png)
30
-
31
-
32
-
33
-
34
-## PCB layout
35
-
36
-- autoroute - by [[kicad-plugin-dat]]
37
-
38
-
39
-
40
-## PCB Info
41
-
42
-commom layers
43
-
44
-| layers | explain | CN |
45
-| -------------- | ------------------ | ------ |
46
-| edge.cuts | board edge layer | č¾¹ę”†å±‚ |
47
-| F/B Silkscreen | Silkscreen layer | äøå°å±‚ |
48
-| F/B Mask | Mask layer | 阻ē„Šå±‚ |
49
-| F/B Paste | solder Paste layer | é””č†å±‚ |
50
-| F/B Cu | copper layer | 铜ē®”层 |
51
-
52
-* F for front and B for back
53
-
54
-## PCB init setup
55
-
56
-![](2023-12-11-00-04-17.png)
57
-
58
-- ē½‘ē»œēŗæ宽
59
-- 钻孔å°ŗåÆø
60
-- ē½‘ę ¼ 1.0 mm
61
-- ē¼©ę”¾
62
-
63
-## Layout setup
64
-
65
-Simply Only use Trace x.CU, Silkscreen layer x.Silkscreen, and Edge.Cuts
66
-
67
-![](2025-04-29-16-22-13.png)
68
-
69
-
70
-## routing PCB
71
-
72
-![](2025-04-29-16-11-14.png)
73
-
74
-![](2025-04-29-16-11-39.png)
75
-
76
-
77
-## Modify PCB
78
-
79
-
80
-## Filled Zones (ground pour)
81
-
82
-Edit - Fill All Zones (B or Ctrl+B)
83
-
84
-
85
-### Optimized the Text
86
-
87
-Optimize the text size of the desginators
88
-
89
-![](2025-05-12-13-02-00.png)
90
-
91
-text width and height 0.6 mm
92
-
93
-## export gerber
94
-
95
-output folder
96
-
97
- for the current folder == ./
98
- for the sub folder "gerber" in current folder == ./gerber
99
-
100
-
101
-## export info
102
-
103
-
104
-layer
105
-- x.Mask
106
-- x.Fab
107
-- Edge.Cuts
108
-![alt text](95e854b5209f226b023ebe7765500e9.png)
... ...
\ No newline at end of file
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fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kidcad-workflow-dat/kicad-sch-dat/kicad-sch-dat.md
... ...
@@ -1,35 +0,0 @@
1
-
2
-# kicad-sch-dat
3
-
4
-
5
-
6
-### add symbol
7
-
8
-- search based on components type and footprint
9
-
10
-![](2024-10-06-16-39-37.png)
11
-
12
-- ctrl+D duplicate the symbol
13
-
14
-- [[kicad-symbol-dat]]
15
-
16
-### mutiple assign the value
17
-
18
-![](2024-10-09-17-15-09.png)
19
-
20
-
21
-
22
-### sort network classes network
23
-
24
-- schematic setup -> net classes
25
-
26
-
27
-
28
-
29
-### assign the footprints
30
-
31
-![](2024-09-18-01-41-13.png)
32
-
33
-- add symbols and assign footprint
34
- - enter "E" for properties, and assign the footprint
35
-
fab-PCB-dat/PCB-dat/EDA-dat/kicad-dat/kidcad-workflow-dat/kicad-workflow-dat.md
... ...
@@ -1,15 +0,0 @@
1
-
2
-# kicad work flow
3
-
4
-- prerequisite shortcuts - https://docs.kicad.org/7.0/en/kicad/kicad.html
5
-
6
-
7
-- [[kicad-sch-dat]] -> [[kicad-pcb-dat]]
8
-
9
-
10
-
11
-## ref
12
-
13
-- [[PCB-fab-dat]]
14
-
15
-- [[kicad-workflow]] - [[kicad]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/EDA-dat/lceda-dat/lceda-dat.md
... ...
@@ -1,21 +0,0 @@
1
-
2
-# easyeda.com-dat
3
-
4
-
5
-
6
-- easyeda.com is a web-based EDA tool that allows users to design and simulate electronic circuits and PCBs. It provides a user-friendly interface and a wide range of features for both beginners and experienced designers.
7
-
8
-- lceda.com
9
-
10
-- pro.easyeda.com
11
-
12
-- support import [[altium-design-dat]] file .pcbdoc
13
-
14
-- support output [[gerber-dat]] file
15
-
16
-
17
-
18
-
19
-## ref
20
-
21
-- [[EDA-dat]]
fab-PCB-dat/PCB-dat/EDA-dat/protel-dat/protel-dat.md
... ...
@@ -1,13 +0,0 @@
1
-
2
-# protel-dat
3
-
4
-- SCH
5
-- PCB
6
-- DDB
7
-
8
-
9
-
10
-
11
-## ref
12
-
13
-- [[protel]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/EDA-simulation-dat/EDA-simulation-dat.md
... ...
@@ -1,49 +0,0 @@
1
-
2
-# EDA-simulation-dat
3
-
4
-## software
5
-
6
-| Software | Features & Use Case | Free Version Available? |
7
-| ---------------------- | ---------------------------------------------------------------- | ------------------------------- |
8
-| **LTspice** | Powerful SPICE simulator for analog circuits (by Analog Devices) | āœ… Free |
9
-| **KiCad** | Open-source PCB design and SPICE simulation | āœ… Free |
10
-| **Altium Designer** | Industry-standard PCB design and simulation | āŒ Paid (Trial available) |
11
-| **Proteus** | Combines schematic capture, PCB design, and simulation | āŒ Paid (Demo available) |
12
-| **EasyEDA** | Online-based PCB design and simulation | āœ… Free |
13
-| **Multisim** | Advanced SPICE simulation with real-time analysis | āŒ Paid (Free for students) |
14
-| **OrCAD PSpice** | High-end analog and mixed-signal simulation | āŒ Paid (Lite version available) |
15
-| **Fusion 360 (Eagle)** | PCB design with simulation tools (by Autodesk) | āœ… Free for hobbyists |
16
-
17
-- [[kicad-simulation-dat]] - [[eagle-simulation-dat]]
18
-
19
-
20
-## ngspice
21
-
22
-- [manual](https://ngspice.sourceforge.io/docs/ngspice-manual.pdf)
23
-
24
-
25
-https://ngspice.sourceforge.io/ngspice-eeschema.html#BipAmp
26
-
27
-
28
-## PSpice
29
-
30
-- PSpice (OrCAD Capture).
31
-- LTspice
32
-
33
-
34
-- [[LM358-dat]]
35
-
36
-
37
-## online simulation
38
-
39
-https://www.circuitlab.com/editor/#?id=7pq5wm&from=homepage
40
-
41
-support: [[amplifier-dat]], [[NE555-dat]], [[comparator-dat]], [[logic-gate-dat]], ...
42
-
43
-
44
-- [[circuit-lab-dat]]
45
-
46
-## ref
47
-
48
-
49
-- [[EDA-dat]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/EDA-simulation-dat/circuit-lab-dat/circuit-lab-dat.md
... ...
@@ -1,12 +0,0 @@
1
-
2
-# circuit-lab-dat
3
-
4
-- [[amplifier-dat]]
5
-
6
-- [Low Pass Active Filter](https://www.circuitlab.com/editor/#?id=z84zq5)
7
-
8
-
9
-
10
-## ref
11
-
12
-- [[EDA-simulation-dat]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/PCB-accesories-dat/PCB-accesories-dat.md
... ...
@@ -1,25 +0,0 @@
1
-
2
-# PCB-accesories-dat
3
-
4
-- [[heatsink-dat]]
5
-
6
-- [[magnetic-screw-dat]]
7
-
8
-- PCB stand == [[PMP1036-dat]] - [[PMP1037-dat]]
9
-
10
-- hexgon spacer == [[PMP1033-dat]] == https://www.electrodragon.com/product/common-used-m3-hexgon-spacing-bar-screw-kit/
11
-
12
-- [[PMP1016-dat]] - [[PMP1019-dat]] - [[PMP1021-dat]] == https://www.electrodragon.com/product/m3-brazz-bolt-different-length-available/
13
-
14
-- PCB electric isolation
15
-
16
-- äø‰é˜²ę¼† == Conformal Coating
17
-
18
-
19
-
20
-
21
-
22
-
23
-## ref
24
-
25
-- [[PCB-dat]] - [[rover-dat]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/PCB-accesories-dat/magnetic-screw-dat/2024-02-17-14-20-10.png
... ...
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fab-PCB-dat/PCB-dat/PCB-accesories-dat/magnetic-screw-dat/2024-02-17-14-27-40.png
... ...
Binary files a/fab-PCB-dat/PCB-dat/PCB-accesories-dat/magnetic-screw-dat/2024-02-17-14-27-40.png and /dev/null differ
fab-PCB-dat/PCB-dat/PCB-accesories-dat/magnetic-screw-dat/2024-02-17-14-28-07.png
... ...
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fab-PCB-dat/PCB-dat/PCB-accesories-dat/magnetic-screw-dat/magnetic-screw-dat.md
... ...
@@ -1,26 +0,0 @@
1
-
2
-# magnetic-screw-dat
3
-
4
-![](2024-02-17-14-20-10.png)
5
-
6
-## 1317-M3
7
-- diameter 13mm, height 17mm
8
-- drill - M3
9
-
10
-![](2024-02-17-14-27-40.png)
11
-
12
-## 1313-M4
13
-
14
-![](2024-02-17-14-28-07.png)
15
-
16
-
17
-
18
-## Demo video
19
-
20
-https://www.youtube.com/shorts/bYAMpQTe3k0
21
-
22
-
23
-
24
-## ref
25
-
26
-- [[PCB-accesories-dat]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/PCB-dat.md
... ...
@@ -1,42 +0,0 @@
1
-
2
-# PCB-dat
3
-
4
-- [[PCB-design-dat]] - [[PCB-make-dat]]
5
-
6
-
7
-## editing
8
-
9
-- [[tools-PCB-dat]] - [[soldering-dat]]
10
-
11
-- [[desoldering-dat]]
12
-
13
-
14
-
15
-## fab
16
-
17
-- [[fab-dat]]
18
-
19
-- [[fab-PCB-dat]] - [[PCB-format-dat]] - [[PCB-output-common-error-dat]] - [[PCB-penalization-dat]]
20
-
21
-- [[fab-PCBA-dat]]
22
-
23
-- [[fab-stencil-dat]]
24
-
25
-
26
-
27
-## desgin
28
-
29
-- [[4-layer-dat]] - [[0402-dat]]
30
-
31
-- [[PCB-form-dat]]
32
-
33
-- [[BTB-dat]]
34
-
35
-## ref
36
-
37
-- [[PCB-dat]] - [[PCB-layout-dat]]
38
-
39
-
40
-
41
-
42
-
fab-PCB-dat/PCB-dat/PCB-design-dat/2025-08-28-16-29-41.png
... ...
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fab-PCB-dat/PCB-dat/PCB-design-dat/PCB-design-dat.md
... ...
@@ -1,50 +0,0 @@
1
-
2
-# PCB-design-dat
3
-
4
-## design
5
-
6
-- [[footprint-dat]] - [[thermal-disppation-dat]] - [[heatsink-dat]] - [[PCB-installation-dat]]
7
-
8
-
9
-- [[EDA-dat]] - [[EDA-simulation-dat]]
10
-
11
-- [[test-point-dat]]
12
-
13
-
14
-## special
15
-
16
-- [[flex-PCB-dat]]
17
-
18
-## basic
19
-
20
-### PCB layers
21
-
22
-| design layers | funcs |
23
-| ------------- | -------------------------------- |
24
-| tStop | solder mask stop on top layer |
25
-| bStop | solder mask stop on bottom layer |
26
-
27
-- [[EDA-dat]] - [[fab-pcb-dat]] - [[fab-pcba-dat]]
28
-
29
-## ERC Rules
30
-
31
-| mil | mm |
32
-| --- | ------ |
33
-| 6 | 0.1524 |
34
-| 8 | 0.2032 |
35
-| 10 | 0.254 |
36
-| 12 | 0.3048 |
37
-| 16 | 0.4064 |
38
-
39
-
40
-## experiences
41
-
42
-ground protected crystals for [[RP2040-dat]] - [[RPI-dat]]
43
-
44
-![](2025-08-28-16-29-41.png)
45
-
46
-
47
-
48
-## ref
49
-
50
-- [[PCB-dat]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/PCB-design-dat/PCB-installation-dat/PCB-installation-dat.md
... ...
@@ -1,8 +0,0 @@
1
-
2
-# PCB-installation-dat
3
-
4
-- [[hexgon-spacing-dat]]
5
-
6
-## magnetic snapping
7
-
8
-- [[PMP1037-dat]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/PCB-design-dat/PCB-layout-dat/2024-11-13-19-18-09.png
... ...
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fab-PCB-dat/PCB-dat/PCB-design-dat/PCB-layout-dat/2024-11-13-19-18-21.png
... ...
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fab-PCB-dat/PCB-dat/PCB-design-dat/PCB-layout-dat/PCB-layout-dat.md
... ...
@@ -1,13 +0,0 @@
1
-
2
-# PCB-layout-dat
3
-
4
-## vertical or 45-degree connectors
5
-
6
-![](2024-11-13-19-18-09.png)
7
-
8
-![](2024-11-13-19-18-21.png)
9
-
10
-
11
-## ref
12
-
13
-- [[PCB-dat]] - [[PCB-layout-dat]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/PCB-design-dat/footprint-dat/SOP8-150-dat/SOP8-150-dat.md
... ...
@@ -1,4 +0,0 @@
1
-
2
-# SOP8-150-dat
3
-
4
-- - width = 3.81 mm = 150 mil
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/PCB-design-dat/footprint-dat/SOP8-200-dat/2024-08-29-01-56-56.png
... ...
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fab-PCB-dat/PCB-dat/PCB-design-dat/footprint-dat/SOP8-200-dat/SOP8-200-dat.md
... ...
@@ -1,6 +0,0 @@
1
-
2
-# SOP8-200-dat.md
3
-
4
-- width = 5.08 mm
5
-
6
-![](2024-08-29-01-56-56.png)
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/PCB-design-dat/test-point-dat/test-point-dat.md
... ...
@@ -1,31 +0,0 @@
1
-
2
-# test-point-dat
3
-
4
-- small batch production can use multimeter to do the test
5
-
6
-add points like
7
-
8
-for power supply - [[power-dat]]
9
-
10
-- VBUS
11
-- 3V3
12
-- GND
13
-
14
-[[epaper-dat]]
15
-
16
-- GDR
17
-- RESET
18
-- VCOM
19
-- PREVGL
20
-- PREVGH
21
-
22
-
23
-- VCOM: Usually between -2V and -3V (sometimes adjustable, check your moduleā€™s datasheet).
24
-- PREVGL: Negative voltage, often around -15V to -20V.
25
-- PREVGH: Positive voltage, often around +15V to +20V.
26
-
27
-VOM
28
-
29
-PRE-VGL == -20V
30
-
31
-PRE-VGH == 20V
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/PCB-design-dat/thermal-disppation-dat/thermal-disppation-dat.md
... ...
@@ -1,44 +0,0 @@
1
-
2
-# thermal-disppation-dat
3
-
4
-- [[heatsink-dat]]
5
-
6
-## āš™ļø Key Factors
7
-
8
-The current-carrying capacity of a 2.54mm (0.1 inch) wide PCB trace depends on:
9
-
10
-- **Copper thickness** (measured in oz/ftĀ²)
11
-- **Temperature rise allowed**
12
-- **Trace location** (internal vs. external)
13
-
14
----
15
-
16
-## šŸ“Š General Guidelines (Based on IPC-2221)
17
-
18
-| Copper Thickness | Trace Type | Temp Rise | Approx. Max Current |
19
-|------------------|----------------|-----------|----------------------|
20
-| 1 oz (35Āµm) | External trace | 10Ā°C | ~2.6 A |
21
-| 1 oz (35Āµm) | External trace | 20Ā°C | ~3.8 A |
22
-| 2 oz (70Āµm) | External trace | 20Ā°C | ~5.0ā€“6.0 A |
23
-| 1 oz (35Āµm) | Internal trace | 20Ā°C | ~2.0ā€“2.5 A |
24
-
25
-> šŸ“ Rule of thumb: For **1 oz copper**, every **1mm width** can safely carry **~1 A** (for external traces and ~10ā€“20Ā°C temp rise).
26
-
27
----
28
-
29
-## šŸ§  Tips
30
-
31
-- Use **wider traces or thicker copper** if higher current is needed.
32
-- Consider **thermal relief**, **via stitching**, or **multiple layers** for better performance.
33
-- For high currents (>5 A), use **solid copper pours** or **bus bars**.
34
-
35
----
36
-
37
-## šŸ› ļø Example
38
-
39
-For a **2.54mm wide**, **1 oz copper** external trace with **20Ā°C rise**:
40
-- Safe current = ~3.5ā€“4.0 A
41
-
42
-## ref
43
-
44
-- [[PCB-design-dat]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/PCB-form-dat/PCB-form-dat.md
... ...
@@ -1,8 +0,0 @@
1
-
2
-# PCB-form-dat
3
-
4
-- [[mini-PCIE-dat]]
5
-
6
-## ref
7
-
8
-- [[PCB-dat]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/PCB-tools-dat/2025-05-16-14-18-42.png
... ...
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fab-PCB-dat/PCB-dat/PCB-tools-dat/PCB-cleaner-dat/PCB-cleaner-dat.md
... ...
@@ -1,60 +0,0 @@
1
-
2
-# PCB-cleaner-dat
3
-
4
-## PCB-cleaner-dat
5
-
6
-### Product Usage Instructions
7
-
8
-Product dimensions and specifications
9
-
10
-**Ultrasonic Cleaning:** Pour the board cleaner into the ultrasonic cleaner, place the PCB board or workpiece to be cleaned inside, turn on the machine, and clean for 4-6 minutes. Then, ventilate and dry for 5-10 minutes.
11
-
12
-**Immersion Cleaning:** Pour this product into a container, immerse the PCB board, then use a brush to scrub it clean, and finally air dry.
13
-
14
-**Spot Cleaning:** Wet a brush or lint-free cloth with this product and directly scrub the oily area. Repeat the scrubbing several times, then air dry.
15
-
16
-**Brush Cleaning:** Pour out this product, soak a brush or lint-free cloth, and then wipe the item that needs cleaning.
17
-
18
-
19
-## Recommended Eco-Friendly and Cost-Effective PCB Cleaner
20
-
21
-### āœ… Recommended Product: Isopropyl Alcohol (IPA, concentration ā‰„ 99%)
22
-
23
-#### šŸ”¹ Features
24
-
25
-- **Eco-Friendly:** Evaporates cleanly with no residue; biodegradable
26
-- **Low Toxicity:** Safer than strong solvents like acetone or trichloroethylene
27
-- **Effective Cleaning:** Removes flux, grease, dust effectively
28
-- **Affordable:** Inexpensive and widely available
29
-- **Versatile:** Suitable for most PCBs and electronic components
30
-
31
-#### šŸ”¹ Precautions
32
-
33
-- Flammable ā€“ keep away from open flames
34
-- Ensure good ventilation during use
35
-- Choose ā‰„99% anhydrous IPA (electronic grade)
36
-
37
----
38
-
39
-### šŸ†š Common PCB Cleaner Comparison Table
40
-
41
-| Product Name | Eco-Friendliness | Price | Cleaning Power | Conductive | Notes |
42
-|-----------------------|------------------|-----------|----------------|------------|-----------------------------------------|
43
-| Isopropyl Alcohol (IPA) | ā˜…ā˜…ā˜…ā˜…ā˜† | ā˜…ā˜…ā˜…ā˜…ā˜… | ā˜…ā˜…ā˜…ā˜…ā˜† | No | Best value, widely applicable |
44
-| Water-Based Cleaner | ā˜…ā˜…ā˜…ā˜…ā˜… | ā˜…ā˜…ā˜…ā˜…ā˜† | ā˜…ā˜…ā˜…ā˜…ā˜† | No | Safe for equipment, slightly weaker |
45
-| Acetone | ā˜…ā˜…ā˜†ā˜†ā˜† | ā˜…ā˜…ā˜…ā˜…ā˜† | ā˜…ā˜…ā˜…ā˜…ā˜… | No | Strong but harsh, can damage plastics |
46
-| Trichloroethylene | ā˜…ā˜†ā˜†ā˜†ā˜† | ā˜…ā˜…ā˜…ā˜†ā˜† | ā˜…ā˜…ā˜…ā˜…ā˜… | No | Toxic, environmentally restricted |
47
-
48
----
49
-
50
-### āœ… Summary Recommendation
51
-
52
-> If youā€™re looking for **eco-friendly + affordable + convenient**, the best option is:
53
->
54
-> ### šŸ‘‰ High-Purity Isopropyl Alcohol (99% IPA)
55
-> Available in bulk or spray form; can be diluted slightly if needed.
56
-
57
-
58
-## ref
59
-
60
-- [[PCB-cleaner]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-dat/PCB-tools-dat/PCB-tools-dat.md
... ...
@@ -1,36 +0,0 @@
1
-
2
-# tools-PCB-dat
3
-
4
-## modification tools
5
-
6
-- cutting tools == [[PSO1060-dat]], shortly cutt the PCB trace
7
-
8
-- mini drill bits == [[PTO1036-dat]], drill little holes to disconnect the PCB trace
9
-
10
-![](2025-05-16-14-18-42.png)
11
-
12
-
13
-## wires
14
-
15
-- [[flywire-dat]] - [[jumper-wire-dat]] - [[cable-dat]] - [[awg-wires-dat]]
16
-
17
-
18
-
19
-
20
-## other tools
21
-
22
-- [[hot-gun-glue-dat]] - [[glue-dat]]
23
-
24
-## cleaner
25
-
26
-- [[PCB-cleaner-dat]]
27
-
28
-
29
-## soldering rack
30
-
31
-[Soldering Iron Wires Rack w/cleaning slots R2](https://www.electrodragon.com/product/casting-metal-soldering-rack/) - [[PSOS010-dat]]
32
-
33
-
34
-## ref
35
-
36
-- [[tools-dat]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-format-dat/2024-07-31-17-27-05.png
... ...
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fab-PCB-dat/PCB-format-dat/PCB-format-dat.md
... ...
@@ -1,11 +0,0 @@
1
-
2
-# PCB-format-dat
3
-
4
-## Common gerber files for (in a .zip)
5
-
6
-![](2024-07-31-17-27-05.png)
7
-
8
-
9
-
10
-
11
-- [[PCB-format]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-output-common-error-dat/35-10-14-18-07-2023.png
... ...
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fab-PCB-dat/PCB-output-common-error-dat/PCB-output-common-error-dat.md
... ...
@@ -1,11 +0,0 @@
1
-
2
-# PCB common error dat
3
-
4
-- [[PCB-format-dat]]
5
-
6
-
7
-### missing layer for production: no stop mask
8
-
9
-![](35-10-14-18-07-2023.png)
10
-
11
-
fab-PCB-dat/PCB-penalization-dat/56-08-14-18-07-2023.png
... ...
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fab-PCB-dat/PCB-penalization-dat/PCB-penalization-dat.md
... ...
@@ -1,35 +0,0 @@
1
-# Penalization
2
-
3
-
4
-
5
-## methods
6
-
7
-
8
-
9
-#### Castellated holes
10
-
11
-Castellated holes, please make sure your board are designed correctly: Place holes, add V-cuts, etc
12
-
13
-![](56-08-14-18-07-2023.png)
14
-
15
-
16
-
17
-# penalization-dat
18
-
19
-- [[many-penalization-examples-dat]]
20
-
21
-
22
-## ref
23
-
24
-- [[stamp-holes-dat]]
25
-
26
-- [[ę‹¼ęæ]]
27
-
28
-
29
-
30
-
31
-
32
-## obseleted
33
-
34
-* [http://dl.electrodragon.com/k/index.php?share/file&user=1&sid=wsIZnGKW 1. Eagle penalize and export gerber file]
35
-* [http://dl.electrodragon.com/k/index.php?share/file&user=1&sid=eKTRh7b3 2. detailed panelized tutorial]
fab-PCB-dat/PCB-penalization-dat/many-penalization-examples-dat/2025-05-16-16-55-09.png
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fab-PCB-dat/PCB-penalization-dat/many-penalization-examples-dat/2025-05-16-16-55-21.png
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fab-PCB-dat/PCB-penalization-dat/many-penalization-examples-dat/2025-05-16-16-55-31.png
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fab-PCB-dat/PCB-penalization-dat/many-penalization-examples-dat/2025-05-16-16-55-39.png
... ...
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fab-PCB-dat/PCB-penalization-dat/many-penalization-examples-dat/2025-05-16-16-56-27.png
... ...
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fab-PCB-dat/PCB-penalization-dat/many-penalization-examples-dat/many-penalization-examples-dat.md
... ...
@@ -1,27 +0,0 @@
1
-
2
-# many-penalization-examples-dat
3
-
4
-## eg1. - [[OPM1175-dat]]
5
-
6
-- [[OPM1175-dat]]
7
-
8
-![](2025-05-16-16-55-09.png)
9
-
10
-![](2025-05-16-16-55-21.png)
11
-
12
-![](2025-05-16-16-55-31.png)
13
-
14
-![](2025-05-16-16-55-39.png)
15
-
16
-PCB Grooving gap = 1mm, drill hole == 0.3mm
17
-
18
-![](2025-05-16-16-56-27.png)
19
-
20
-
21
-## eg2. -
22
-
23
-
24
-
25
-## ref
26
-
27
-- [[fab-dat]]
... ...
\ No newline at end of file
fab-PCB-dat/PCB-standards-dat/PCB-standards-dat.md
... ...
@@ -1,95 +0,0 @@
1
-
2
-# PCB-standards-dat
3
-
4
-- 8 mil = 0.2 mm
5
-- 10 mil = 0.25 mm (common used)
6
-- 12 mil = 0.3048 mm
7
-- 14 mil = 0.3556 mm
8
-
9
-| category | Standards | 0.2 mm | 10 mil | Note. CN |
10
-| --------- | ---------------------- | -------------- | ------ | -------- |
11
-| clearance | Wire -> Wire, Pad, Via | 0.2 mm | | |
12
-| clearance | Wire -> edge | 0.2 mm | | |
13
-| Size | Signal Width | 0.2 mm | | |
14
-| Size | Minimum Drill | 0.25 mm | | |
15
-| Miscs. | roundness | 0.15 mm @ 100% | | |
16
-| Miscs. | Mask | 0.1mm @ 100% | | |
17
-| Misc. | Min. Diameter | | | |
18
-| Misc. | Annular Ring | | | |
19
-
20
-
21
-
22
-
23
-
24
-### Other Manufacturing Limits
25
-
26
-| Type | Specs | Note |
27
-| -------------------------------- | -------------------------------------- | ------------------------------------ |
28
-| PCB Type | FR-4 from KB company | - |
29
-| Maximum size | 1200mm X1200mm | more than 550mm prices will increase |
30
-| Dimensions accuracy of board | Ā± 0.2mm | - |
31
-| Thickness range | 0.40~3mm | - |
32
-| Thickness tolerance | Ā±10% | - |
33
-| Dielectric thickness | 0.075 - 5.00mm | - |
34
-| Copper thickness | 17um - 100um | default 1OZ 35um, 0.035mm |
35
-| Drilling Hole | 0.3mm - 6.30mm | - |
36
-| Drilling Hole Tolerances | 0.08mm | - |
37
-| Drilling Hole position tolerance | 0.09mm | - |
38
-| Pour hypotenuse | 30~60 Ā° | - |
39
-| Color | red, blue, green, white, yellow, black | default green\|- |
40
-| Soldering Pads Plating | HASL, ROSH (lead-free), ENIG | |
41
-
42
-
43
-
44
-
45
-
46
-
47
-## Manufacturing capability
48
-Please adapte this to your own "DRC(Design Rule Check)" tool, to make sure your board reach the manufacturing limits.<br />
49
-
50
-### Common-Used Design Ruled DRC
51
-
52
-| Name | Min. inch (mm) | Max. | Eagle CAD Default |
53
-| ----------------------------------- | ------------------- | ------------------ | ----------------- |
54
-| Trace Width/Spacing | 6/6 mils (0.15 mm) | - | 10/8 mils |
55
-| Via/Hole Spacing | 6 mils (0.15 mm) | - | 8 mils |
56
-| Drilling hole (vias) | 10 mils (0.25 mm) * | 250 mils (6.35 mm) | Sizes 24 mils |
57
-| Min. stop mask | 4 mils (0.1 mm) | - | Masks 4 mils |
58
-| Min. copper/trace to ground spacing | 8 mils (0.2 mm) | - | 40 mils |
59
-
60
-
61
-### Note
62
-* Minimum milling width of grooves is 0.8mm
63
-* A lot numbers of vias may cost extra
64
-* Dimension: Any irregular shape should be treated as a rectangular, with maximum size.
65
-* Board test:Ā  fully tested by fly probes.
66
-
67
-#### Half-Hole/Impedance
68
-- Half-Hole + $20, if you need this please contact first or write note in order.
69
-- Impedance + $60
70
-
71
-### What do not support
72
-* Four layers boards
73
-* Blind holes (not through holes).
74
-
75
-
76
-
77
-
78
-### Extra PCB Technics
79
-
80
-| Type | Description | Category |
81
-| ---------------------- | ------------------------------------------------------------------------------------------------------------------------------------------- | ---------------------------- |
82
-| Lead free ROHS | free for samples, extra cost for batch production | Soldering Pads Plate Technic |
83
-| ENIG | Gold immersion on pads, better look, better soldering, etc | Soldering Pads Plate Technic |
84
-| Faster PCB in 30 Hours | PCB Manufacturing will be finished in one and half day, not including shipping and handing time. Cost is 42 USD. Can not with ENIG service. | Express PCB |
85
-| Faster PCB in 53 Hours | PCB Manufacturing will be finished in two and half day, not including shipping and handing time. Cost is 21 USD. | Express PCB |
86
-| 2oz copper thickness | Get better heat dissipation for your board, example like A4988 board. | - |
87
-| Board thickness | Free from 0.6 till 1.6 mm, extra cost need for 0.4 and 2.0 mm thickness. (available thickness 0.4 0.6 0.8 1.0 1.2 1.6 2.0) | - |
88
-
89
-
90
-
91
-
92
-
93
-## ref
94
-
95
-- [[kicad-dat]]
... ...
\ No newline at end of file
fab-PCB-dat/fab-PCB-dat.md
... ...
@@ -1,87 +0,0 @@
1
-
2
-# fab-PCB-dat
3
-
4
-
5
-- legacy wiki page - https://w.electrodragon.com/w/Category:PCB
6
-
7
-## PCB production design
8
-
9
-- [[PCB-penalization-dat]]
10
-
11
-## output PCB file
12
-
13
-- [[PCB-output-common-error-dat]]
14
-
15
-- to understand the manufacturing capability, see here - [[PCB-standards-dat]]
16
-
17
-- check correct output format - [[PCB-format-dat]]
18
-
19
-
20
-
21
-### Order self-Check List
22
-
23
-- layer: 1, 2, 4, 6, 8
24
-- Output Type: Single, Continious(As file), Countinious (By our engineer)
25
-- Size: ? x ? mm
26
-- Quantity: ? pcs
27
-- Technic Edge (If single, or penalized by us) : ? mm, up/bottom, left/right, all, none
28
-- Penalize Rules (If penalized by us): ? x ? pcs
29
-- Thickness: 0.6, 0.8, 1.0, 1.2, 1.6, 2.0 (+100), 2.5 (N/A now)
30
-- Copper Thickness: 1oz, 2oz
31
-- Min. Trace Width/Spacing: 6/6 mil, 5/5 mil (+15), 4/4 mil (+65), 3/3 mil (N/A now)
32
-- Min. Drill: 0.3 mm, 0.25 mm (+30), 0.2 mm (+30),
33
-- Stop Mask Color: Green, Blue, Red, Yellow, Black, Near-Black, White
34
-- Character Color: White, Black
35
-- Stop-mask Cover: Vias covered, Vias not covered, If gerber files defined then follow gerber!
36
-- Solder Pads Plate: Lead, Lead Free (+30), Gold Plated (+100)
37
-- Test Numbers: 0,
38
-- Test Method: Sample Free,
39
-- Half-hole: None Default, Yes
40
-- Impedence: None Default, Yes
41
-
42
-
43
-
44
-
45
-### FAQ
46
-
47
-##### Stop Mask on the Vias?
48
-Yes, stop mask will cover the vias, but not the pads, please be aware on this point.
49
-
50
-##### What is dimension requirement of Drilling?
51
-- Drilling as not padding diameter range from 0.3 mm to infinity
52
-- Drilling as pads diameter range from 0.3 mm to 6mm
53
-- Drill shape doesn't not support rectangular, most of other shape are no problem.
54
--
55
-##### What is the price for different board thickness?
56
-For 0.8 - 1.6 mm thickness board, the price is default, without this arrange there will be an extra charge.
57
-
58
-##### What is the price for board over size 10*10 CM
59
-Please contact us to get a quote.
60
-
61
-##### What is lead time of this service
62
-For 5*5 cm and 10*10 cm sample PCBs, the lead time is 4-6 days that not including Sunday. For more than 50pcs 10*10 cm batch or similar to that, we will have 2-3 days extra for production.
63
-
64
-
65
-
66
-
67
-== PCB Production Cost List ==
68
-
69
-## quantity setup
70
-
71
-The quantity must be a multiple of 5.
72
-
73
-| PCB quantity | penalization (e.g.) | total |
74
-| ------------ | ------------------- | ----- |
75
-| 5 | 8 | 40 |
76
-| 10 | 8 | 80 |
77
-| 15 | 8 | 120 |
78
-| 20 | 8 | 160 |
79
-| 25 | 8 | 200 |
80
-| 30 | 8 | 240 |
81
-
82
-
83
-## ref
84
-
85
-- [[PCBA-dat]]
86
-
87
-- [[fab-PCB-dat]]
fab-PCBA-dat/fab-Stencil-DAT/fab-stencil-dat.md
... ...
@@ -11,7 +11,7 @@
11 11
other un-common size frameless
12 12
13 13
- 10 x 15 cm
14
-
14
+- 15 x 20 cm
15 15
16 16
17 17
### all size framed
... ...
@@ -25,6 +25,19 @@ other un-common size frameless
25 25
26 26
27 27
28
+25 X 30 CM
29
+30 X 40 CM
30
+37 X 47 CM
31
+42 X 52 CM
32
+45 x 55 CM
33
+40 x 60 CM
34
+40 x 70 CM
35
+40 x 80 CM
36
+58 X 58 CM
37
+55 x 65 CM
38
+
39
+
40
+
28 41
| no. | area | usable | price | weight |
29 42
| --- | ------------------- | -------- | ------- | ------ |
30 43
| 1 | 37 x 47 | 19 x 29 | 71 RMB | 1.5KG |