Board-dat/NWI/NWI1125-DAT/NWI1125-DAT.md
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-# NWI 1125
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-
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-## The look
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-
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-![](15-33-17-12-12-2022.png)
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-
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-![](22-33-17-12-12-2022.png)
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-
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-### modifications from NWI1124 -> NWI1125
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-
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-- removed reset pin
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-- removed IO 0 pull up
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-- removed IO 2 pull up
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-- removed EN pull up
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-- removed IO 15 pull down
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-
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-
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-
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-### map pins
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-
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-- [[ESP-12F-DAT]]
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-- [[ESP-C3-12F-DAT]]
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-
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-#### [[ESP-12F-DAT]] (nwi1124) = [[ESP-C3-12F-DAT]] (nwi1125)
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-
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- - IO12 = IO4 = Blue
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- - IO13 = IO5 = Green
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- - IO14 = IO3 = White
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- - IO15 = IO8 = Red
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- - IO02 = IO10 = WS2812
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- - IO00 = IO9 = RF
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-
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-
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-#### [[ESP-12F-DAT]] (nwi1124) = [[ESPC2-12-DAT]] (nwi112x)
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-
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-
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-pin definitions :
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-
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-
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-| L: function | L: pins | note |
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-| ----------- | ------- | ----- |
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-| ADC | IO0 | |
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-| EN | IO1 | |
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-| IO12 | IO4 | blue |
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-| IO13 | IO5 | green |
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-| IO14 | IO3 | white |
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-| IO16 | IO2 | |
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-| RST | EN | |
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-| VCC | VCC | |
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-
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-
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-| R: function | R: pins | note |
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-| ----------- | ------- | ------ |
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-| GND | GND | |
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-| IO0 | IO9 | RF |
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-| IO15 | IO6 | red |
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-| IO2 | IO7 | ws2812 |
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-| IO4 | IO10 | |
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-| IO5 | IO18 | |
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-| RXD | RXD | |
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-| TXD | TXD | |
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-
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-
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-## Code
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-- please change the wifi hotspot name to match in the code
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-- control by web URL in your browser
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+
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+
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+
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+# NWI1125-dat
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+
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+## The look
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+
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+![](15-33-17-12-12-2022.png)
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+
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+![](22-33-17-12-12-2022.png)
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+
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+### modifications from NWI1124 -> NWI1125
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+
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+- removed reset pin
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+- removed IO 0 pull up
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+- removed IO 2 pull up
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+- removed EN pull up
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+- removed IO 15 pull down
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+
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+
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+
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+### map pins
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+
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+- [[ESP-12F-DAT]]
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+- [[ESP-C3-12F-DAT]]
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+
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+#### [[ESP-12F-DAT]] (nwi1124) = [[ESP-C3-12F-DAT]] (nwi1125)
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+
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+ - IO12 = IO4 = Blue
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+ - IO13 = IO5 = Green
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+ - IO14 = IO3 = White
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+ - IO15 = IO8 = Red
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+ - IO02 = IO10 = WS2812
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+ - IO00 = IO9 = RF
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+
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+
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+#### [[ESP-12F-DAT]] (nwi1124) = [[ESPC2-12-DAT]] (nwi112x)
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+
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+
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+pin definitions :
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+
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+
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+| L: function | L: pins | note |
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+| ----------- | ------- | ----- |
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+| ADC | IO0 | |
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+| EN | IO1 | |
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+| IO12 | IO4 | blue |
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+| IO13 | IO5 | green |
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+| IO14 | IO3 | white |
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+| IO16 | IO2 | |
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+| RST | EN | |
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+| VCC | VCC | |
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+
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+
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+| R: function | R: pins | note |
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+| ----------- | ------- | ------ |
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+| GND | GND | |
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+| IO0 | IO9 | RF |
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+| IO15 | IO6 | red |
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+| IO2 | IO7 | ws2812 |
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+| IO4 | IO10 | |
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+| IO5 | IO18 | |
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+| RXD | RXD | |
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+| TXD | TXD | |
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+
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+
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+## Code
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+- please change the wifi hotspot name to match in the code
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+- control by web URL in your browser
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- https://github.com/Edragon/Arduino-ESP32/tree/master/Sketchbook/BSP/NWI1125/webserver-path-1-ESP32-C3-12F
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Board-dat/SDR/SDR1125-dat/SDR1125-dat.md
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# SDR1125-dat.md
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+- [[kicad-dat]]
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+
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- [[SDR1125-dat]] - [[CRSF-dat]] - [[ELRS-dat]]
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- [[PCB-design-dat]]
PCB-dat/EDA-dat/kicad-dat/kidcad-workflow-dat/kicad-pcb-dat/2026-07-08-01-08-26.png
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Binary files /dev/null and b/PCB-dat/EDA-dat/kicad-dat/kidcad-workflow-dat/kicad-pcb-dat/2026-07-08-01-08-26.png differ
PCB-dat/EDA-dat/kicad-dat/kidcad-workflow-dat/kicad-pcb-dat/kicad-pcb-dat.md
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+## net and netclasses
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+
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+![](2026-07-08-01-08-26.png)
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+
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## ref
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- [[kicad-dat]]
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PCB-dat/PCB-dat.md
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- [[test-point-dat]]
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+
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+## specs
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+
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+- [[PCB-solder-mask-dat]] - [[PCB-dat]] - [[PCB-design-dat]] - [[PCB-vias-dat]]
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+
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## PCB edit
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- [[fab-PCB-desoldering-dat]] - [[PCB-fix-dat]]
PCB-dat/PCB-design-dat/PCB-design-dat.md
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- [[PCB-design-dat]] - [[power-dat]]
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+
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+
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## special
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- [[PCB-flex-dat]]
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+### Current Capacity Table (1 oz Copper)
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+| Trace Width | Layer Location | Current Cap @ $10^\circ\text{C}$ Rise | Current Cap @ $20^\circ\text{C}$ Rise |
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+| :--- | :--- | :--- | :--- |
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+| **0.5 mm** (~20 mils) | **External** (Surface) | **~1.1 A** | **~1.6 A** |
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+| | **Internal** (Inner) | ~0.6 A | ~0.9 A |
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+| **1.0 mm** (~40 mils) | **External** (Surface) | **~1.8 A** | **~2.6 A** |
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+| | **Internal** (Inner) | ~1.1 A | ~1.5 A |
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+| **2.0 mm** (~80 mils) | **External** (Surface) | **~3.0 A** | **~4.2 A** |
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+| | **Internal** (Inner) | ~1.7 A | ~2.4 A |
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+
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+### 10A peak current handle
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+Transient **peak current** (pulses, spikes, or brief bursts), a **2.0 mm wide, 1 oz copper trace can absolutely handle 10A**.
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+However, if "peak" means a sustained heavy load that lasts for more than a few seconds, it will struggle. Here is how it breaks down based on the duration of that 10A current:
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+### 1. Short Pulses / Transient Peaks (Safe)
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+If the 10A current consists of short pulses (e.g., motor startup spikes, switching transients, or RC ESC/inrush currents) lasting from **a few milliseconds up to 1–2 seconds**, the trace will handle it easily.
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+* **Why:** Copper has thermal mass. It takes time for the energy from a brief pulse to heat up the trace. As long as the pulse ends before the copper reaches its maximum temperature, it won't damage the board.
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+
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+### 2. Continuous or Long Peaks (Not Safe)
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+If the 10A load is sustained for **longer than 5 to 10 seconds** at a time, a standard 2.0 mm 1 oz external trace will overheat.
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+* **The Math:** To safely carry 10A *continuously* on 1 oz copper without exceeding a standard $20^\circ\text{C}$ temperature rise, you would typically need an external trace width of around **5.0 mm to 6.0 mm**.
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+* Running 10A continuously through a 2.0 mm trace would cause a massive temperature rise—likely exceeding **$80^\circ\text{C}$ to $100^\circ\text{C}$ above ambient**. This risks damaging the FR4 substrate, lifting the trace off the board, or causing system instability.
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+
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+---
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+
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+### How to Make a 2.0 mm Trace Handle 10A Safely
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+If your layout forces you to stick to a 2.0 mm trace width, but you need to support long or frequent 10A peaks, use these hardware workarounds:
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+* **Increase Copper Weight to 2 oz ($70\ \mu\text{m}$):** Bumping your PCB fabrication settings to 2 oz copper immediately doubles the cross-sectional area. A 2.0 mm trace on 2 oz copper handles continuous currents much closer to 5–6A, making 10A peaks significantly safer.
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+* **Expose the Trace and Add Solder:** Design the PCB with the solder mask window removed over that specific 2.0 mm track. During assembly, a thick layer of solder can be flowed over the exposed copper, drastically increasing its thickness and lowering resistance.
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+* **Route on Both Top and Bottom Layers:** Duplicate the 2.0 mm trace on both the top and bottom layers in parallel, stitching them together with multiple via holes to split the current evenly (5A per layer).
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## ref
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- [[PCB-dat]]
PCB-dat/PCB-solder-mask-dat/PCB-solder-mask-dat.md
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+# PCB-solder-mask-dat
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+- [[PCB-solder-mask-dat]] - [[PCB-dat]] - [[PCB-design-dat]] - [[PCB-vias-dat]]
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+KiCad treats the mask layers—F.Mask (Front Mask) and B.Mask (Back Mask)—as negative layers.
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+Anything you draw on F.Mask or B.Mask represents an opening in the solder mask.
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+If you draw a line or a polygon on F.Mask right over a copper track on F.Cu, KiCad will tell the factory to leave that area bare.
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+## ref
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+
PCB-dat/PCB-vias-dat/PCB-vias-dat.md
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+# PCB-vias-dat
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+default minimal vias == 0.3 mm
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fab-dat/fab-PCB-dat/PCB-vias-dat/PCB-vias-dat.md
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-# PCB-vias-dat
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-
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-default minimal vias == 0.3 mm
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+
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+# PCB-vias-dat
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+
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+- [[PCB-solder-mask-dat]] - [[PCB-dat]] - [[PCB-design-dat]] - [[PCB-vias-dat]]
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+
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+
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+default minimal vias == 0.3 mm
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+
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+## The Via Rule of Thumb
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+As a reliable hardware engineering benchmark for a standard **0.3 mm hole diameter** with standard **$1\ \text{oz}$ ($35\ \mu\text{m}$) hole wall plating**:
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+* **1 Via** safely handles **~1A to 1.5A** of continuous current at a $10^\circ\text{C}$ temperature rise.
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+Therefore, to safely pass a **10A peak**, you should use:
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+* **Minimum:** **4 to 5 vias** (if the 10A is a very brief, occasional pulse).
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+* **Recommended Safely:** **7 to 10 vias** stitched together in a cluster or grid.
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+
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+---
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+
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+### Via Current Capacity Table
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+If you change the size of your vias, their current capacity changes. Here is a quick reference table for common prototyping via sizes (assuming standard 1 oz / $35\ \mu\text{m}$ copper plating and a conservative $10^\circ\text{C}$ rise):
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+| Drill/Hole Size | Outer Pad Diameter | Current Capacity (Per Via) | Vias Needed for 10A Peak |
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+| :-------------------- | :----------------- | :------------------------- | :----------------------- |
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+| **0.3 mm** (~12 mils) | 0.6 mm (~24 mils) | **~1.2 A** | **8 to 10 vias** |
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+| **0.5 mm** (~20 mils) | 0.9 mm (~35 mils) | **~1.9 A** | **5 to 6 vias** |
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+| **0.8 mm** (~31 mils) | 1.4 mm (~55 mils) | **~2.8 A** | **3 to 4 vias** |
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+
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+---
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+
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+### Best Practices for Layout in KiCad
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+When splitting 10A across multiple vias, how you place them matters just as much as how many you use:
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+1. **Arrange them in a Grid/Cluster:** Place the vias close together right where the top trace transitions to the bottom trace. Arrange them in a tight $2\times4$ or $3\times3$ grid.
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+2. **Ensure Equal Sharing:** Place the vias symmetrically across the width of the 2.0 mm trace. If you line them up in a single file line matching the direction of the current, the first few vias will take the brunt of the current, while the ones at the back won't do much work.
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+3. **Keep the Tracks Wide:** Make sure the copper traces leading *into* and *out of* the via cluster on both layers are wide enough to handle their share of the current.
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+