Board-dat/DOD/DODS044-dat/DODS044-dat.md
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@@ -2,8 +2,11 @@
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# DODS044 dat
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+https://www.electrodragon.com/product/altera-cpld-epm240-epm570-dev-board/
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+
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## ref
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- [[EPM570-dat]] - [[DODS044]]
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+- [[CPLD-dat]] - [[FPGA-dat]]
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Board-dat/DPR/DPR1077-dat/DPR1077-dat.md
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@@ -24,6 +24,9 @@ JTAG protocol communication is a very vulnerable protocol, please avoid interfer
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- if any communication error happened, reconnect the programmer, and restart Quartus II software.
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+## driver
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+
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+- [[USB-Blaster-driver.rar]]
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## ref
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Board-dat/DPR/DPR1077-dat/USB-Blaster-driver.rar
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Binary files /dev/null and b/Board-dat/DPR/DPR1077-dat/USB-Blaster-driver.rar differ
Tech-dat/FPGA-dat/FPGA-dat.md
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@@ -1,16 +0,0 @@
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-
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-# FPGA-dat
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-
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-## common board
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-
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-- https://tinyfpga.com/
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-
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-- Basys 3 - https://digilent.com/reference/programmable-logic/basys-3/start?redirect=1
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-
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-
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-
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-## ref
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-
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-- [[logic-dat]]
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-
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-- [[tech-dat]]
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Tech-dat/MCU-dat/CPLD-dat/cpld-dat.md
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@@ -1,10 +1,81 @@
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# cpld dat
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+## boards
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+
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+- [[DODS044-dat]] - [[DODS042-dat]]
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+
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+
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+
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+## programmer
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+
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+- https://www.electrodragon.com/product/usb-blaster-ed-revsion-altera-cpldfpga-programmer/
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+
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+- [[DPR1077-dat]]
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+
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+
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+
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+## software
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+
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+- Quartus 11.0
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+
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+## chips
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+
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- [[EPM240-dat]] - [[EPM570-dat]]
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-## MAX II
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+
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+### Xilinx
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+
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+* XC9572XL
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+
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+XILINX - CPLD
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+
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+* XC9536xl - 10
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+* XL9572xl - 12
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+
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+* XC2C64 - 22
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+* XC2C32A - 32/44 pin
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+
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+
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+### Intel / Altera
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+
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+* EPM240
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+* EPM570
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+
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+https://www.altera.com/products/cpld/max-series/max-ii/overview.html
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+
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+#### MAX II
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+
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+* EPM240 - 8
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+* EPM570
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+
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+* EPM3032
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+* EPM3064
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+
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+
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+### MAX II
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https://www.altera.com/products/cpld/max-series/max-ii/overview.html
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-https://www.electrodragon.com/w/Altera_CPLD_EPM240_EPM570_Dev._Board
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\ No newline at end of file
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+https://www.electrodragon.com/w/Altera_CPLD_EPM240_EPM570_Dev._Board
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+
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+
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+### Altera
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+
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+* max1010m02
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+
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+
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+### Lattice
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+
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+* XO3
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+
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+
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+### AGM
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+
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+* AG1280Q48
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+* AG576SL100 - 18
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+
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+
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+## ref
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+
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+- [[CPLD-dat]] - [[FPGA-dat]]
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Tech-dat/MCU-dat/FPGA-dat/FPGA-dat.md
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@@ -0,0 +1,41 @@
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+# FPGA-dat
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+
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+
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+## codes
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+
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+https://github.com/Edragon/FPGA_EP4
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+
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+https://github.com/Edragon/FPGA_MAX10-2
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+
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+https://github.com/Edragon/FPGA_MAX10-1
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+
12
+https://github.com/Edragon/FPGA_SDK
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+- Altera/EP2C
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+
15
+https://github.com/Edragon/FPGA_HDK
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+
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+https://github.com/Edragon/FPGA_DOCS
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+
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+https://github.com/Edragon/fpga_max10
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+
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+
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+
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+
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+## common board
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+
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+- https://tinyfpga.com/
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+
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+- Basys 3 - https://digilent.com/reference/programmable-logic/basys-3/start?redirect=1
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+
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+
31
+
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+## ref
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+
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+- [[logic-dat]]
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+
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+- [[tech-dat]]
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+
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+
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+## ref
40
+
41
+- [[CPLD-dat]] - [[FPGA-dat]]
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