camera

+| Voltage Type | set | Voltage Range |

+| ------------ | ------ | ------------- |

+## pins

+

+- [[OV2640-dat]]

+

+| NO. | SYMBOL |

+| --- | ------ |

+| 1 | STORBE |

+| 2 | AGND |

+| 3 | SIO_D |

+| 4 | AVDD |

+| 5 | SIO_C |

+| 6 | RESET |

+| 7 | VSYNC |

+| 8 | PWDN |

+| 9 | HREF |

+| 10 | DVDD |

+| 11 | DOVDD |

+| 12 | Y9 |

+| 13 | XCLK |

+| 14 | Y8 |

+| 15 | DGND |

+| 16 | Y7 |

+| 17 | PCLK |

+| 18 | Y6 |

+| 19 | Y2 |

+| 20 | Y5 |

+| 21 | Y3 |

+| 22 | Y4 |

+| 23 | Y1 |

+| 24 | YO |

+| pin | camera | ESP32 |

+| --- | ------ | --------- |

+| 1 | NC | |

+| 2 | AGND | GND |

+| 3 | SDA | IO8 SDA |

+| 4 | AVDD | 2V8 |

+| 5 | SCL | IO9 SCL |

+| 6 | RST | pull-up |

+| 7 | VSYNC | IO1 |

+| 8 | PWDN | pull-down |

+| 9 | HSYNC | IO2 |

+| 10 | DVDD | 1V5 |

+| 11 | DOVDD | 2V8 |

+| 12 | Y9 | IO4 |

+| 13 | XMCLK | IO5 |

+| 14 | Y8 | IO6 |

+| 15 | GND | GND |

+| 16 | Y7 | IO7 |

+| 17 | PCLK | 32K_P |

+| 18 | Y6 | IO14 |

+| 19 | Y2 | 32K_N |

+| 20 | Y5 | IO17 |

+| 21 | Y3 | IO18 |

+| 22 | Y4 | IO21 |

+| 23 | NC | |

+| 24 | NC | |

+| 25* | GND | GND |

+

+

+

+

+

+Connector

+

+24Pins Description for - [[OV3660-dat]]

+

+| Pin No. | Name | Description |

+| ------- | -------- | ---------------------- |

+| 01 | NC | - |

+| 02 | AGND | Analog Ground |

+| 03 | SIO_D | Serial Data |

+| 04 | AVDD_28 | Analog Voltage 2.8V |

+| 05 | SIO_C | Serial Clock |

+| 06 | RESET | Reset |

+| 07 | VSync | Vertical Sync |

+| 08 | PWDN | Power Down |

+| 09 | HS(HREF) | Horizontal Sync (HREF) |

+| 10 | DVDD_15 | Digital Voltage 1.5V |

+| 11 | DOVDD | Digital Output Voltage |

+| 12 | D9 | Data Bit 9 |

+| 13 | MCLK | Master Clock |

+| 14 | D8 | Data Bit 8 |

+| 15 | DGND | Digital Ground |

+| 16 | D7 | Data Bit 7 |

+| 17 | PCLK | Pixel Clock |

+| 18 | D6 | Data Bit 6 |

+| 19 | D2 | Data Bit 2 |

+| 20 | D5 | Data Bit 5 |

+| 21 | D3 | Data Bit 3 |

+| 22 | D4 | Data Bit 4 |

+| 23 | NC | - |

+| 24 | NC | - |

+

+

+

+- DVP Y2 ~ Y9

+- DVP_PCLK

+- XMCLK

+- DVP_HREF

+- DVP_VSYNC

+- I2C SDA / SCL

+

+Power supply 2V8 and 1V5

+

+

+

+

+- [[LDO-dat]]

+

+

+

+

+

+

+- [[OV3660-dat]] - [[OV2640-dat]] - [[OV5640-dat]] - [[omnivision-dat]] - [[camera-DVP-dat]]

+## 24 pins compare

+

+- [[OV2640-dat]]

+

+## pins

+

+- [[OV2640-dat]]

+

+| NO. | SYMBOL |

+| --- | ------ |

+| 1 | STORBE |

+| 2 | AGND |

+| 3 | SIO_D |

+| 4 | AVDD |

+| 5 | SIO_C |

+| 6 | RESET |

+| 7 | VSYNC |

+| 8 | PWDN |

+| 9 | HREF |

+| 10 | DVDD |

+| 11 | DOVDD |

+| 12 | Y9 |

+| 13 | XCLK |

+| 14 | Y8 |

+| 15 | DGND |

+| 16 | Y7 |

+| 17 | PCLK |

+| 18 | Y6 |

+| 19 | Y2 |

+| 20 | Y5 |

+| 21 | Y3 |

+| 22 | Y4 |

+| 23 | Y1 |

+| 24 | YO |

+

+- [[OV3660-dat]]

+

+| pin | camera | ESP32 |

+| --- | ------------ | --------- |

+| 1 | NC | |

+| 2 | AGND | GND |

+| 3 | SDA / SIO_D | IO8 SDA |

+| 4 | AVDD | 2V8 |

+| 5 | SCL / SIO_C | IO9 SCL |

+| 6 | RESET | pull-up |

+| 7 | VSYNC | IO1 |

+| 8 | PWDN | pull-down |

+| 9 | HSYNC / HREF | IO2 |

+| 10 | DVDD | 1V5 |

+| 11 | DOVDD | 2V8 |

+| 12 | Y9 | IO4 |

+| 13 | XMCLK / XCLK | IO5 |

+| 14 | Y8 | IO6 |

+| 15 | GND | GND |

+| 16 | Y7 | IO7 |

+| 17 | PCLK | 32K_P |

+| 18 | Y6 | IO14 |

+| 19 | Y2 | 32K_N |

+| 20 | Y5 | IO17 |

+| 21 | Y3 | IO18 |

+| 22 | Y4 | IO21 |

+| 23 | NC | |

+| 24 | NC | |

+| 25* | GND | GND |

+# DVP-display-dat

+

+no DVP display, only [[DVP-camera-dat]]

+

+## RGB Parallel Interface vs DVP Interface

+

+| Feature | RGB Parallel Interface (Display MCU Interface) | DVP Interface (Digital Video Port, Camera) |

+|----------------------|-----------------------------------------------|--------------------------------------------|

+| Data Direction | MCU → Display | Camera → MCU |

+| Data Lines | D0~D7 or D0~D15 (pixel data) | D0~D7 or D0~D9 (pixel data) |

+| Control Signals | WR / RD / RS / CS / DE / HSYNC / VSYNC | PCLK / HREF / VSYNC |

+| Timing | MCU-controlled writes (typical 8080 / 6800) | Camera outputs fixed pixel timing |

+| Use Case | TFT LCD display | CMOS camera module |

+| Interface Type | Parallel | Parallel |

+| Similarity | Both use multi-line parallel pixel transfer | Both use multi-line parallel pixel transfer|

+

+**Summary:**

+- DVP is a parallel output interface from a camera; MCU or FPGA captures image data.

+- The RGB parallel interface is a display input; MCU or FPGA drives the panel.

+- They are electrically similar, but timing and purpose differ.

+

+## Can DVP Be Used as a Display Interface?

+

+- Strictly speaking, DVP (Digital Video Port) was defined as a camera output interface for MCU/FPGA reception.

+- However, in practice some low-resolution or embedded display modules can accept DVP-style input:

+ - These modules integrate a small controller that converts incoming DVP pixel timing into the panel drive.

+ - The MCU or FPGA sends pixel data following DVP timing directly to the module.

+

+### Characteristics

+- Physical signals are similar: PCLK, VSYNC, HSYNC/HREF, data lines D0~Dn.

+- Timing still follows DVP style (one pixel per PCLK edge).

+- Common in low-resolution embedded TFT modules (e.g. 2.4", 2.8" TFT LCD).

+

+### Notes / Caveats

+- You cannot treat a high-resolution raw TFT RGB panel as a DVP display module.

+- The driving MCU/FPGA must generate DVP-like streaming timing, different from 8080/6800 register/data bus write cycles.

+- Datasheets will usually state “DVP input” or “Camera interface for MCU” if such usage is supported.

+

+**Conclusion:**

+- DVP is fundamentally a camera (image sensor) interface.

+- Some display modules are DVP-compatible, but you must adhere to DVP streaming timing and control behavior.

+

+# MIPI vs DVP Interface Comparison

+

+| Feature | MIPI (DSI / CSI) | DVP (Digital Video Port) |

+| --------------------- | ----------------------------------------------------- | ------------------------------------------------- |

+| **Type** | High-speed **serial** differential signaling | **Parallel** CMOS/TTL signaling |

+| **Data Lines** | 1–4 (sometimes 8) differential lanes + clock | Multiple parallel data lines (8, 10, 12, 16 bits) |

+| **Clock** | Embedded in protocol (Data lanes use DDR with strobe) | Separate dedicated pixel clock (PCLK) |

+| **Signal Standard** | MIPI D-PHY / C-PHY (low-voltage differential) | CMOS/TTL single-ended logic |

+| **Data Rate** | Up to several Gbps per lane | Typically < 150 MHz pixel clock |

+| **Wiring Complexity** | Fewer wires (high-speed pairs) | Many wires (one per data bit + sync) |

+| **Pins** | Very few (e.g., 4–10 total) | Many (e.g., 10–20+ total) |

+| **Sync Signals** | Embedded in packet protocol | HSYNC, VSYNC required |

+| **Protocol Layer** | Uses packet-based protocol (like networking) | Raw pixel data per clock |

+| **Power Consumption** | Lower per bit transferred (but high-speed) | Higher due to many single-ended lines |

+| **Typical Use** | Smartphones, tablets, high-res displays/cameras | Simple camera modules, low-cost LCDs |

+| **Example Devices** | MIPI-DSI display panels, MIPI-CSI2 camera sensors | OV7670 camera, parallel RGB LCD panels |

+

+

+

+

+

+

+

+**DVP** in the display context usually refers to the **Digital Video Port** interface. - [[parallel-display-dat]]

+It’s a **parallel interface** commonly used in cameras, simple LCDs, or microcontroller-driven displays.

+

+## How it works

+

+

+- Transfers **pixel data** in parallel (8, 16, or 24 data lines, depending on color depth).

+- Uses **synchronization signals**:

+ - **HSYNC** (Horizontal Sync) – signals the start of a new line

+ - **VSYNC** (Vertical Sync) – signals the start of a new frame

+ - **PCLK** (Pixel Clock) – latches each pixel’s data

+- Can work with formats like **RGB565**, **RGB888**, or **YUV422**.

+

+## Key Characteristics

+1. **Simple protocol** – no complex packetization (unlike MIPI-DSI).

+2. **Lower speed** – parallel clock typically in the tens of MHz.

+3. **More pins needed** – due to multiple parallel data lines.

+4. **Used in MCUs and simple SoCs** – no need for high-speed serializers.

+

+## Common Uses

+

+

+- Cheap TFT LCD modules with MCU controllers

+- CMOS camera modules with parallel output

+- Low-resolution displays in industrial or hobby projects

+

+## Comparison (DVP vs MIPI-DSI)

+

+| Feature | DVP (Digital Video Port) | MIPI-DSI |

+| ------------- | -------------------------- | ----------------------------------- |

+| Data Transfer | Parallel (8–24 data lines) | High-speed serial (2–4 lanes) |

+| Speed | Tens of MHz | Hundreds of MHz to Gbps |

+| Pin Count | High | Low |

+| Complexity | Simple | Complex, packetized |

+| Use Case | Simple displays, cameras | High-res smartphone/tablet displays |

+

+## SCH

+

+- [[F133-dat]]

+

+8-bit Y2 ~ Y9 // HSYNC + VSYNC + PCLK + XCLK + SCL + SDA + **RST

+

+

+

+

+

+## DVP Display 22-Pin Interface

+

+6 bit version

+

+| Pin No. | Symbol | Description |

+| ------- | ------ | ------------------------ |

+| 1 | VCC | Power supply |

+| 2 | GND | Ground |

+| 3 | RST | Reset |

+| 4 | CS | Chip select |

+| 5 | SCL | Serial clock |

+| 6 | VS | Vertical sync |

+| 7 | HS | Horizontal sync |

+| 8 | DE | Data enable |

+| 9 | DLCK | Data clock (pixel clock) |

+| 10 | SDA | Serial data |

+| 11 | K | Backlight control (LEDK) |

+| 12 | A | Backlight control (LEDA) |

+| 13 | D0 | Data bit 0 |

+| 14 | D1 | Data bit 1 |

+| 15 | D2 | Data bit 2 |

+| 16 | D3 | Data bit 3 |

+| 17 | D4 | Data bit 4 |

+| 18 | D5 | Data bit 5 |

+| 19 | NC | - |

+| 20 | NC | - |

+| 21 | NC | - |

+| 22 | NC | - |

+

+

+## ref

+

+- [[parallel-display-dat]]

+# camera-DVP-dat

+

+- [[LDO-2CH-dat]]

+

+- [[OV2640-dat]] - [[OV3660-dat]] - [[OV560-dat]] - [[omnivision-dat]]

+

+

+

+## DVP Pin Mapping & Functional Equivalents

+

+In DVP (Digital Video Port) camera sensors, many pins have synonymous names depending on whether the manufacturer uses industry-standard or proprietary labels.

+

+| Standard Protocol | Camera Sensor Label | Function Description |

+| :---------------- | :------------------ | :------------------------------------------------------------------------------------------------------- |

+| **SDA** | **SIO_D** | **Serial Data:** The data line for the I2C-compatible SCCB interface used to configure camera registers. |

+| **SCL** | **SIO_C** | **Serial Clock:** The clock signal for the I2C-compatible configuration interface. |

+| **HSYNC** | **HREF** | **Horizontal Reference:** High when a valid row of pixels is being transmitted. |

+| **XMCLK / MCLK** | **XCLK** | **External Clock:** The master heartbeat (usually 24MHz) provided by the MCU to drive the sensor. |

+

+---

+

+### Critical Technical Nuances

+

+#### 1. SCCB vs. I2C (SIO_D / SIO_C)

+While **SIO_D/C** is physically identical to I2C, it often uses the **SCCB** (Serial Camera Control Bus) protocol.

+* **Compatibility:** Most modern MCU I2C peripherals work fine, but some older sensors do not generate an "Acknowledge" (ACK) bit.

+* **Fix:** If your MCU throws an I2C error, try disabling "ACK checking" in your driver code.

+

+#### 2. Timing Reference (HSYNC vs. HREF)

+* **HSYNC** is technically the pulse *between* lines.

+* **HREF** is a "gate" signal that stays HIGH while data is valid on the Y2-Y9 (D0-D7) pins.

+* **Wiring:** Connect your MCU's HSYNC input directly to the Sensor's HREF pin.

+

+

+

+#### 3. The Master Clock (XCLK)

+* The sensor will **not** respond to I2C (SIO_D) commands until it receives a stable XCLK signal.

+* **Pro-tip for Rover V2:** Keep XCLK and PCLK traces as short as possible. High-speed clock lines can create EMI that might interfere with your sensitive **BMI323** IMU or **DRV8701** gate drivers if they are routed too closely.

+

+#### 4. Power Sequencing

+1. Apply Power (DVDD, AVDD, DOVDD).

+2. Start **XCLK**.

+3. Pulse **RESET** low.

+4. Begin **SIO_D/C** configuration.

+

+

+

+## **Can Y0/Y1 be NC?**

+ Yes. This effectively truncates a 10-bit or 12-bit sensor output to 8-bit.

+

+* **Key Technical Rules:**

+ 1. **Bit Alignment:** You must map the Sensor MSBs to the Processor D-pins.

+ * Sensor Y9 -> Processor D7

+ * Sensor Y8 -> Processor D6

+ * ...

+ * Sensor Y2 -> Processor D0

+ 2. **Truncation:** Y0 and Y1 are the LSBs (fine detail). Leaving them NC simply discards the lowest 4 levels of pixel data, which is standard for most 8-bit MCU/SoC interfaces.

+

+* **Important Considerations:**

+ * **Register Configuration:** You MUST configure the camera sensor (via I2C/SCCB) to output in 8-bit mode (e.g., YUV422 or RGB565).

+ * **EMI Mitigation:** While NC works, terminating with a high-value pull-down resistor can improve signal integrity if you notice noise.

+ * **Clocking:** The PCLK frequency remains identical; ensure your timing constraints in your firmware account for the 8-bit throughput.

+

+* **Comparison Table (10-bit vs 8-bit):**

+

+| Feature | 10-bit (Full) | 8-bit (Truncated) |

+| :------------ | :----------------------- | :-------------------- |

+| Dynamic Range | 1024 levels | 256 levels |

+| Compatibility | High (Requires 10+ pins) | Universal (8-pin bus) |

+| Use Case | High-end imaging | Navigation/Tracking |

+

+

+

+## ref

+

+- [[camera-dat]]

+-

+

+# CSI-dat

+

+**CSI (Camera Serial Interface)**

+

+Uses a 15-pin MIPI CSI-2 ribbon cable connector.

+

+Designed for official Raspberry Pi Camera Modules.

+

+Offers high-speed data transfer directly to the Raspberry Pi’s GPU.

+

+Supports Raspberry Pi Camera Module v1, v2, and v3, as well as the High-Quality Camera.

+

+Provides lower latency and better performance compared to USB.

+

+

+## SCH 1 DSI + CSI interface

+

+

+

+## ref

+

+- [[DSI-dat]] - [[CSI-dat]]

+

+- [[camera-dat]]

+## DVP vs. MIPI-CSI Camera Interfaces

+

+- [[camera-interface-dat]] - [[camera-DVP-dat]] - [[camera-CSI-dat]]

+

+| Feature | **DVP (Parallel)** | **MIPI-CSI (Serial)** |

+| :-------------- | :--------------------------- | :------------------------------ |

+| **Data Flow** | All bits (8-12) sent at once | Data sent in high-speed packets |

+| **Wiring** | High pin count (15+ wires) | Low pin count (4-10 wires) |

+| **Signal Type** | Standard CMOS (Single-ended) | Differential Pairs (Low Noise) |

+| **Complexity** | Simple; easy to debug | High; requires dedicated PHY |

+| **Best For** | **Rover V2**, ESP32, STM32 | Raspberry Pi, Jetson, 4K Video |

+

+---

+

+### Key Takeaways for Your Project

+

+* **DVP (What you are using):** Uses pins like **Y0-Y9**. You can leave **Y0/Y1 NC** to treat it as an 8-bit bus. It is perfect for microcontrollers but sensitive to motor noise (EMI) from your **DRV8701**.

+* **CSI:** Used for high-definition AI tasks. It uses "Lanes" instead of individual data bits, making it much harder to wire manually but better for long cables.

+

+

+[[OmniVision-dat]] == [[camera-DVP-dat]] - [[camera-CSI-dat]]

+- [[OV3660-dat]] - [[OV2640-dat]] - [[OV5640-dat]]

+- [[OV7670-dat]] - [[OV7725-dat]]

+

+