Chip-cn-dat/allwinner-dat/F133-dat/F133-dat.md
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@@ -7,6 +7,8 @@
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- [[FPC-dat]] - [[switch-dat]]
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+- [[RTL8723-dat]]
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+
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## version
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Chip-dat/Realtek-dat/RTL8723-dat/RTL8723-dat.md
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# RTL8723-dat
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+- [[wifi-dat]] + [[bluetooth-dat]]
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+
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![](2025-07-13-22-32-52.png)
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![](2025-07-13-22-33-38.png)
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- [[allwinner-dat]]
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+- [[ipex-dat]]
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+
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## ref
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- [[realtek-dat]]
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\ No newline at end of file
PCB-dat/4-layer-dat/4-layer-dat.md
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+
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+# 4-layer-dat
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+
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+The typical lamination order for a 4-layer PCB is:
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+
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+- Top Layer: Signal layer
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+- Inner Layer 1: Power plane (e.g., VCC or GND)
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+- Inner Layer 2: Ground plane (e.g., GND or VCC)
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+- Bottom Layer: Signal layer
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+
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+## lamination order
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+
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+"4-layer PCB stack-up:
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+
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+- Top Layer: Signal
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+- Inner Layer 1: Power (VCC)
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+- Inner Layer 2: Ground (GND)
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+- Bottom Layer: Signal
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+
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+Please follow this lamination order for manufacturing."
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+
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+
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+
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+## ref
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+
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+- [[PCB-dat]]
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\ No newline at end of file
PCB-dat/PCB-dat.md
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- [[desoldering-dat]]
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+
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+
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## fab
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- [[fab-dat]]
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- [[fab-stencil-dat]]
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-
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+- [[4-layer-dat]]
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## ref
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Tech-dat/antenna-dat/ipex-dat/2025-07-14-01-28-59.png
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Binary files /dev/null and b/Tech-dat/antenna-dat/ipex-dat/2025-07-14-01-28-59.png differ
Tech-dat/antenna-dat/ipex-dat/ipex-dat.md
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@@ -4,4 +4,16 @@
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Types: left 1st Gen, middle 4st Gen., right soldering wire.
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-![](2024-02-18-17-09-06.png)
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\ No newline at end of file
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+![](2024-02-18-17-09-06.png)
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+
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+
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+## footprint
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+
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+- IPEX-SMD_HC-RF-IPEX0303-01 == HC-RF-IPEX0303-01
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+
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+![](2025-07-14-01-28-59.png)
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+
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+
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+## ref
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+
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+- [[antenna-dat]]
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\ No newline at end of file