PCB-dat/EDA-dat/eaglecad-dat/eaglecad-dat.md
... ...
@@ -1,6 +1,10 @@
1 1
2 2
# eagle-CAD-dat
3 3
4
+
5
+
6
+- [[PCB-design-dat]]
7
+
4 8
- https://github.com/Edragon/Eagle-CAD-dat
5 9
- ~~https://github.com/Edragon/CAD-Eagle-part~~
6 10
... ...
@@ -68,4 +72,6 @@ thermal only for holes
68 72
69 73
- [[eagle-cad]]
70 74
71
-- [[MPC1073-dat]]
... ...
\ No newline at end of file
0
+- [[MPC1073-dat]]
1
+
2
+https://forums.autodesk.com/t5/eagle-forum
... ...
\ No newline at end of file
PCB-dat/EDA-dat/kicad-dat/kicad-dat.md
... ...
@@ -56,7 +56,11 @@ alt ctrl F
56 56
57 57
## Features
58 58
59
-- [[reverse-engineering-dat]]
59
+- [[reverse-engineering-dat]] - [[PCB-design-dat]]
60
+
61
+
62
+
63
+
60 64
61 65
## ref
62 66
PCB-dat/PCB-design-dat/DRC-dat/DRC-dat.md
... ...
@@ -1,51 +0,0 @@
1
-
2
-# DRC-dat
3
-
4
-## Board Stackup
5
-
6
-- layer == 2 or 4
7
-
8
-## design
9
-
10
-### contrains
11
-
12
-Copper
13
-
14
-| Constraint | Value mm |
15
-| ------------------------ | -------- |
16
-| Minimum clearance | 0 |
17
-| Minimum track width | 0.1 |
18
-| Minimum connection width | 0 |
19
-| Minimum annular width | 0.05 |
20
-| Minimum via diameter | 0.45 |
21
-| Copper to hole clearance | 0 |
22
-| Copper to edge clearance | 0.1 |
23
-
24
-Holes
25
-
26
-- Minimum through hole: 0.25 mm
27
-- Hole to hole clearance: 0.24 mm
28
-
29
-uVias
30
-
31
-- Minimum uVia diameter: 0.2 mm
32
-- Minimum uVia hole: 0.1 mm
33
-
34
-Silkscreen
35
-
36
-- Minimum item clearance: 0 mm
37
-- Minimum text height: 0.8 mm
38
-- Minimum text thickness: 0.08 mm
39
-
40
-### Pre-defined Sizes
41
-### Teardrops
42
-### Length-tuning Patterns
43
-### Net Classes
44
-### Custom Rules
45
-### Violation Severity
46
-
47
-
48
-## ref
49
-
50
-- [[PCB-design-dat]]
51
-
PCB-dat/PCB-design-dat/PCB-DRC-dat/PCB-DRC-dat.md
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@@ -0,0 +1,51 @@
1
+
2
+# DRC-dat
3
+
4
+## Board Stackup
5
+
6
+- layer == 2 or 4
7
+
8
+## design
9
+
10
+### contrains
11
+
12
+Copper
13
+
14
+| Constraint | Value mm |
15
+| ------------------------ | -------- |
16
+| Minimum clearance | 0 |
17
+| Minimum track width | 0.1 |
18
+| Minimum connection width | 0 |
19
+| Minimum annular width | 0.05 |
20
+| Minimum via diameter | 0.45 |
21
+| Copper to hole clearance | 0 |
22
+| Copper to edge clearance | 0.1 |
23
+
24
+Holes
25
+
26
+- Minimum through hole: 0.25 mm
27
+- Hole to hole clearance: 0.24 mm
28
+
29
+uVias
30
+
31
+- Minimum uVia diameter: 0.2 mm
32
+- Minimum uVia hole: 0.1 mm
33
+
34
+Silkscreen
35
+
36
+- Minimum item clearance: 0 mm
37
+- Minimum text height: 0.8 mm
38
+- Minimum text thickness: 0.08 mm
39
+
40
+### Pre-defined Sizes
41
+### Teardrops
42
+### Length-tuning Patterns
43
+### Net Classes
44
+### Custom Rules
45
+### Violation Severity
46
+
47
+
48
+## ref
49
+
50
+- [[PCB-design-dat]]
51
+
PCB-dat/PCB-design-dat/PCB-customized-dat/PCB-customized-dat.md
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@@ -0,0 +1,16 @@
1
+
2
+
3
+# PCB-customized-dat
4
+
5
+- [[PCB-customized-dat]] - [[PCB-design-dat]] - [[PCB-dat]]
6
+
7
+consider following options
8
+
9
+- add your own logo / watermark / artwork ?
10
+- PCB color ?
11
+
12
+
13
+
14
+
15
+## ref
16
+
PCB-dat/PCB-design-dat/PCB-design-basic-dat/PCB-design-basic-dat.md
... ...
@@ -5,6 +5,15 @@
5 5
- [[pcb-design-basic-dat]] - [[dev-board-dat]] - [[peripherals-dat]]
6 6
7 7
8
+
9
+## silkscreen
10
+
11
+- clear silkscreen for connectors, interface, test points, etc.
12
+- watermark / logo / artwork
13
+
14
+
15
+
16
+
8 17
## LEDs
9 18
10 19
- 电源指示灯 - 用于 检测 电源状态 - [[LED-dat]]
PCB-dat/PCB-design-dat/PCB-design-dat.md
... ...
@@ -5,9 +5,9 @@
5 5
6 6
- [[PCB-design-basic-dat]] - [[PCB-design-stack-dat]] - [[peripherals-dat]] - [[dev-board-dat]]
7 7
8
+- [[reverse-engineering-dat]] - [[PCB-design-dat]]
8 9
9
-
10
-- [[PCB-dat]]
10
+- [[PCB-customized-dat]] - [[PCB-design-dat]] - [[PCB-dat]]
11 11
12 12
13 13
- [[footprint-dat]] - [[thermal-disppation-dat]] - [[heatsink-dat]] - [[PCB-installation-dat]]
PCB-dat/PCB-design-dat/PCB-double-side-dat/PCB-double-side-dat.md
... ...
@@ -0,0 +1,26 @@
1
+
2
+# double-side-PCB-dat
3
+
4
+- [[fab-stencil-double-side]]
5
+
6
+
7
+## General Rules
8
+
9
+| Factor | Rule of Thumb | Reason |
10
+| --------------------------------- | ----------------------------------------------------------------------------- | ---------------------------------------------------------------- |
11
+| **Component size & weight** | **Lighter / smaller SMD components are placed first**, usually on the bottom. | Heavy parts may fall off during second reflow. |
12
+| **Through-hole parts** | Always populated **after reflow** (usually last step). | Reflow ovens are for SMD; THT is wave-soldered or hand-soldered. |
13
+| **BGA, QFN, Fine-pitch ICs** | Usually go on the **primary (top) side**. | Better solder joint reliability and inspection access. |
14
+| **Connectors, mechanical parts** | Preferably on the **primary side**. | Reduces stress during use. |
15
+| **Assembly process optimization** | PCB side with **more components** usually chosen as **first (primary) side**. | Reduces machine setup time and cost. |
16
+
17
+
18
+- [[fab-stencil]]
19
+
20
+
21
+
22
+
23
+
24
+## ref
25
+
26
+- [[double-side-PCB]] - [[PCB-design]]
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\ No newline at end of file
PCB-dat/PCB-design-dat/PCB-footprint-dat/2025-05-29-15-10-00.png
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Binary files /dev/null and b/PCB-dat/PCB-design-dat/PCB-footprint-dat/2025-05-29-15-10-00.png differ
PCB-dat/PCB-design-dat/PCB-footprint-dat/PCB-footprint-dat.md
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@@ -0,0 +1,223 @@
1
+
2
+# footprint-dat.md
3
+
4
+- [[EDA-dat]]
5
+
6
+- [[kicad-dat]] - [[kicad-footprint-dat]]
7
+
8
+- [[fab-PCBA-dat]]
9
+
10
+
11
+
12
+## boards
13
+
14
+- [[CCO3628-dat]] - [[CCO3627-dat]]
15
+
16
+- [[DPR1016-dat]]
17
+
18
+- [[CCO3626-dat]] - [[CCO3629-dat]] - [[prog-socket-SMD2DIP-dat]]
19
+
20
+
21
+## footprints
22
+
23
+- [[PLCC-dat]]
24
+
25
+
26
+## pitch large footprint
27
+
28
+- [[SOP-dat]]
29
+
30
+## pitch 0.8mm
31
+
32
+- [[TQFP-dat]]
33
+
34
+## pitch 0.5mm footprint
35
+
36
+- [[QFN-dat]] - [[WLP-dat]] == [[MAX98357-dat]] - [[BQ51050-dat]]
37
+
38
+- [[QFP-dat]]
39
+
40
+- [[SSOP-dat]]
41
+
42
+
43
+
44
+## pitch 0.4mm footprint
45
+
46
+- pitch 0.5mm [[DF40-dat]]
47
+
48
+
49
+
50
+## common footprint libraries
51
+
52
+- [[nettie-dat]]
53
+- [[test-point-dat]]
54
+- Connector_FFC-FPC
55
+- Connector_PinHeader_1.00mm
56
+- Connector_PinSocket_1.00mm
57
+- Connector_JST
58
+- Connector_Molex
59
+- Jumper
60
+- Connector_Wire
61
+- Package_CSP
62
+
63
+
64
+## IC Package Footprintscategorized by pitch
65
+
66
+
67
+| Pitch (mm) | Package Types & Examples |
68
+|------------|-------------------------------------------------------------------------------------------|
69
+| **0.3 mm** | WLCSP (Wafer Level Chip Scale Package), uBGA (Ultra Fine Pitch BGA), QFN (fine pitch) |
70
+| **0.35 mm**| DFN (small pitch variants), QFN (ultra fine pitch), LGA |
71
+| **0.4 mm** | QFN (fine pitch), CSP (Chip Scale Package), BGA (fine pitch), DFN |
72
+| **0.5 mm** | QFN (common pitch), TQFP (fine pitch), LGA, DFN |
73
+| **0.635 mm** | SSOP (Shrink Small Outline Package), TSSOP (Thin Shrink SOP) |
74
+| **0.8 mm** | QFP (Quad Flat Package), TQFP (standard pitch), LQFP, BGA (medium pitch) |
75
+| **1.0 mm** | QFP (larger pitch), LQFP, PLCC (Plastic Leaded Chip Carrier), SOIC (narrow pitch) |
76
+| **1.27 mm**| SOIC (Small Outline IC), DIP (Dual In-line Package), PLCC |
77
+| **1.5 mm** | Older DIP variants, larger SIP (Single In-line Package) |
78
+| **2.0 mm** | Some DIP, SIP, Power Packages (TO-220 multi-pin) |
79
+| **2.54 mm (0.1")** | Standard DIP (most common), SIP, headers, through-hole connectors |
80
+
81
+
82
+## Methods to Examine Hidden Solder Bridges Under Packages
83
+
84
+| Method | Description | Pros | Cons / Limitations |
85
+|--------------------------------|-----------------------------------------------------------------------------|------------------------------------------|-----------------------------------------|
86
+| **X-Ray Inspection** | Uses 2D or 3D X-ray (AXI/CT) to image solder joints under the package. | Most reliable, can see voids, bridges, opens | Expensive equipment, not DIY friendly |
87
+| **Microscope with Oblique Light** | Tilted inspection around chip edges, sometimes you can see solder "squeeze-out". | Cheap, immediate check | Only shows gross defects near edges |
88
+| **Electrical Continuity Test** | Use multimeter to check resistance between adjacent pins/pads. | Simple, effective for shorts | Cannot detect open joints or cold solder|
89
+| **Boundary Scan (JTAG)** | IC self-tests connectivity if supported. | Automated, precise | Only available if IC has JTAG support |
90
+| **Thermal Camera / IR Imaging**| Power up board, shorts often cause local hot spots. | Non-contact, quick check | Needs power-on, risk of damage |
91
+| **Flying Probe / ICT Test** | Automated test system probes nets for shorts/opens. | Precise, production use | Expensive, setup time |
92
+| **Acoustic Microscopy (SAM)** | Ultrasound imaging can detect voids or poor solder bonding. | High resolution for reliability testing | Very expensive, lab equipment only |
93
+
94
+
95
+For hobbyist / small-lab use:
96
+
97
+**Best option**: Electrical continuity check with a **multimeter** (between power rails, adjacent pins).
98
+
99
+Second best: If you suspect hidden bridges, try **thermal camera** (small USB IR cameras are affordable).
100
+
101
+Pro-level: Use an **X-ray machine** (common in professional PCB assembly houses).
102
+
103
+👉 If you’re debugging **why the IC doesn’t work after reflow**, I’d suggest:
104
+
105
+Check for shorts with multimeter.
106
+
107
+Power briefly, then feel for **overheating** (carefully) or use thermal camera.
108
+
109
+If nothing obvious, suspect **opens (unsoldered pads)**, which can only be 100% confirmed by X-ray or functional testing.
110
+
111
+
112
+
113
+## DIY Methods to Detect Hidden Solder Bridges Under Packages (No X-Ray)
114
+
115
+| Method | How It Works | Notes / Tips |
116
+|--------------------------------|-------------------------------------------------------------------------------|--------------|
117
+| **Multimeter Continuity Check**| With power off, measure resistance between power rails (VCC–GND) and between suspect pins. | If you read ~0Ω or very low resistance, there may be a bridge. |
118
+| **Current-Limited Power Test** | Power board with a bench supply set to current limit (e.g. 50–100mA). If supply immediately hits limit, there’s likely a short. | Use low limit to avoid chip damage. |
119
+| **Thermal Finger Test / IR Camera** | Briefly power on with current limit. A solder bridge often causes a tiny hot spot. | Safer with cheap USB thermal cameras. |
120
+| **Rosin / Alcohol Wetting** | Apply isopropyl alcohol or rosin flux around package edges, then power board. If there is a short, liquid may boil or show bubbles near bridged pads. | Not very precise, but sometimes works. |
121
+| **Resistance Mapping** | Compare resistance between ground and each I/O pin versus a known-good board. | Detects anomalies indirectly. |
122
+| **Functional "Wiggle Test"** | Gently press down or heat package with hot air. If circuit suddenly works or fails, some pads may be bridged or floating. | Risky — only use for debugging prototypes. |
123
+
124
+Practical DIY Workflow
125
+
126
+**First step**: Check resistance between **VCC and GND** before powering. If it’s suspiciously low, suspect a bridge.
127
+
128
+**Second step**: Use **current-limited bench supply** to power on — check for overheating.
129
+
130
+**Third step**: If possible, use **cheap thermal camera** (even phone add-ons) to find hot spots.
131
+
132
+**Last resort**: Rework package with **flux + hot air and reflow** — often fixes hidden bridges without even finding them.
133
+
134
+👉 This way you don’t need expensive X-ray, just a multimeter, alcohol/flux, and maybe a thermal camera.
135
+
136
+
137
+
138
+## general footprint guide
139
+
140
+### overal setup
141
+
142
+| Setting | 1 | 2 | 3 | 4 |
143
+| ------------- | --- | ---- | ----- | -------- |
144
+| Grid Size | 1.0 | 0.5 | 1.27 | 2.54 mm |
145
+| Snap Size | 0.1 | 0.05 | 0.127 | 0.254 mm |
146
+| Alt Snap Size | 0.1 | 0.05 | 0.127 | 0.254 mm |
147
+
148
+
149
+- units == mm
150
+
151
+### create new footprint
152
+
153
+- pad
154
+- layer select
155
+ - for SMD part == top / bottom layer only
156
+ - for THT part == all layer
157
+ - also check the hole size and shape
158
+
159
+
160
+
161
+## generate footprint descriptions
162
+
163
+CAP 4.7UF, 0805, 10%, MLCC, 50V, X5R, ROHS
164
+
165
+RES 1K 5%, 0805, THICK FILM, 150V, 1/8W, ROHS
166
+
167
+Here's a breakdown of the structure:
168
+
169
+- CAP/RES: Component Type (Capacitor or Resistor)
170
+- 4.7UF/1K: Value (4.7 Microfarads or 1 Kiloohm)
171
+- 0805: Package Size (0805 is a standard SMD package size)
172
+- 10%/5%: Tolerance (10% or 5% variation in value)
173
+- MLCC/THICK FILM: Technology or Type (Multi-Layer Ceramic Capacitor or Thick Film Resistor)
174
+- 50V/150V: Voltage Rating (50 Volts or 150 Volts)
175
+- X5R: Dielectric (Specific to capacitors, defines temperature characteristics)
176
+- 1/8W: Power Rating (1/8 Watt, specific to resistors)
177
+- ROHS: RoHS Compliant (Restriction of Hazardous Substances)
178
+
179
+LED SMD VERMELHO, 0805, 2V, 25MA, 624NM, 60MCD, 140°, ROHS
180
+
181
+- "VERMELHO" is Portuguese for red.
182
+- 624nm wavelength corresponds to red light on the visible spectrum.
183
+- Other details like 2V, 25mA, and 60mcd just describe electrical and luminous specs.
184
+
185
+
186
+
187
+
188
+
189
+
190
+
191
+
192
+### Electronic Industries Alliance (EIA)
193
+
194
+
195
+EIA 3528-21 Meaning
196
+
197
+| Section | Description |
198
+| ------- | --------------------------------------------------------------------------------------------------------------- |
199
+| 3528 | Physical size of the component in hundredths of inches: 3.5 mm x 2.8 mm (i.e., 0.138" x 0.110") |
200
+| -21 | Indicates a specific height and pad layout variation within the 3528 size range. Typically means ~2.1 mm height |
201
+
202
+
203
+CRISTAL 12MHz, SMD, 3.2X2.5MM, 18PF, 20PPM, ROHS
204
+
205
+This corresponds to the standard 3225 SMD package (also known as EIA 3225 or 3.2x2.5mm SMD crystal).
206
+
207
+## SOD-123
208
+
209
+SOD-123 is a small SMD package used for diodes, transistors, and other components. It has a footprint of approximately 1.6mm x 0.8mm (0.063" x 0.031") and is commonly used in low-power applications.
210
+
211
+![](2025-05-29-15-10-00.png)
212
+
213
+
214
+
215
+## SOD-323
216
+
217
+
218
+
219
+## ref
220
+
221
+- [[BOM-dat]]
222
+
223
+- [[kicad-pcb-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-design-dat/PCB-footprint-dat/QFN-dat/QFN-dat.md
... ...
@@ -0,0 +1,47 @@
1
+
2
+# QFN-dat
3
+
4
+
5
+## QFN32 table
6
+
7
+| pin | name | note | custom |
8
+| --- | ---- | ---- | ------ |
9
+| 1 | | | |
10
+| 2 | | | |
11
+| 3 | | | |
12
+| 4 | | | |
13
+| 5 | | | |
14
+| 6 | | | |
15
+| 7 | | | |
16
+| 8 | | | |
17
+| 9 | | | |
18
+| 10 | | | |
19
+| 11 | | | |
20
+| 12 | | | |
21
+| 13 | | | |
22
+| 14 | | | |
23
+| 15 | | | |
24
+| 16 | | | |
25
+| 17 | | | |
26
+| 18 | | | |
27
+| 19 | | | |
28
+| 20 | | | |
29
+| 21 | | | |
30
+| 22 | | | |
31
+| 23 | | | |
32
+| 24 | | | |
33
+| 25 | | | |
34
+| 26 | | | |
35
+| 27 | | | |
36
+| 28 | | | |
37
+| 29 | | | |
38
+| 30 | | | |
39
+| 31 | | | |
40
+| 32 | | | |
41
+| pad | | | |
42
+
43
+
44
+
45
+## ref
46
+
47
+- [[footprint-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-design-dat/PCB-footprint-dat/SOP8-150-dat/SOP8-150-dat.md
... ...
@@ -0,0 +1,4 @@
1
+
2
+# SOP8-150-dat
3
+
4
+- - width = 3.81 mm = 150 mil
... ...
\ No newline at end of file
PCB-dat/PCB-design-dat/PCB-footprint-dat/SOP8-200-dat/2024-08-29-01-56-56.png
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PCB-dat/PCB-design-dat/PCB-footprint-dat/SOP8-200-dat/SOP8-200-dat.md
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@@ -0,0 +1,6 @@
1
+
2
+# SOP8-200-dat.md
3
+
4
+- width = 5.08 mm
5
+
6
+![](2024-08-29-01-56-56.png)
... ...
\ No newline at end of file
PCB-dat/PCB-design-dat/PCB-footprint-dat/SSOP-dat/2025-09-29-20-25-04.png
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PCB-dat/PCB-design-dat/PCB-footprint-dat/SSOP-dat/SSOP-dat.md
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1
+
2
+# SSOP-dat
3
+
4
+![](2025-09-29-20-25-04.png)
5
+
6
+
7
+
8
+## 0.635 mm Pitch SSOP
9
+- **Pin pitch (e)**: 0.635 mm
10
+- **Lead width (b)**: 0.18 – 0.30 mm
11
+- **Recommended pad width**: ~0.25 mm
12
+- **Recommended pad length**: 1.30 – 1.50 mm
13
+
14
+## 0.65 mm Pitch SSOP
15
+- **Pin pitch (e)**: 0.65 mm
16
+- **Lead width (b)**: 0.22 – 0.38 mm
17
+- **Recommended pad width**: 0.30 mm (nominal)
18
+- **Recommended pad length**: 1.40 – 1.60 mm
19
+- **Pad-to-pad spacing**: 0.35 mm (center-to-center 0.65 mm minus pad width 0.30 mm)
20
+
21
+
22
+## SSOP-16 (0.635 mm pitch) Stop Mask Guidelines
23
+
24
+- **Copper pad width**: ~0.25 mm (typical)
25
+- **Solder mask expansion**: +0.05 – 0.07 mm per side
26
+- **Mask opening width**: ~0.35 – 0.39 mm
27
+- **Pad-to-pad spacing (center-to-center)**: 0.635 mm
28
+- **Mask dam (between pads)**:
29
+ - 0.635 – (0.25 + 0.25) – (2 × expansion 0.05–0.07)
30
+ - ≈ 0.08 – 0.10 mm left as mask dam
31
+- **Fabrication note**: Some fabs require **≥0.10 mm mask dam**, so if your fab’s capability is 0.10 mm, you are right at the limit.
32
+
33
+
34
+
35
+
36
+## ref
37
+
38
+- [[footprint-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-design-dat/PCB-footprint-dat/TQFP-dat/2025-12-12-17-50-40.png
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PCB-dat/PCB-design-dat/PCB-footprint-dat/TQFP-dat/TQFP-dat.md
... ...
@@ -0,0 +1,47 @@
1
+
2
+# TQFP-dat
3
+
4
+## TQFP32 package
5
+
6
+- [[atmega328-dat]]
7
+
8
+![](2025-12-12-17-50-40.png)
9
+
10
+
11
+## CNV-TQFP32
12
+
13
+![](2026-02-20-17-57-23.png)
14
+
15
+ pin 5 = pin 1
16
+ pin 6 = pin 2
17
+ pin 7 = pin 3
18
+ pin 8 = pin 4
19
+ pin 9 = pin 5
20
+
21
+ pin 22 = pin 18
22
+ pin 23 = pin 19
23
+ pin 24 = pin 20
24
+ pin 25 = pin 21
25
+
26
+
27
+
28
+
29
+
30
+
31
+
32
+
33
+![](2026-02-20-18-03-27.png)
34
+
35
+
36
+
37
+
38
+## ref
39
+
40
+- [[footprint-dat]]
41
+
42
+
43
+
44
+
45
+
46
+
47
+
PCB-dat/PCB-design-dat/PCB-footprint-dat/nettie-dat/2025-09-06-16-31-45.png
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PCB-dat/PCB-design-dat/PCB-footprint-dat/nettie-dat/nettie-dat.md
... ...
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1
+
2
+# nettie-dat
3
+
4
+[[kicad-dat]] - nettie
5
+
6
+![](2025-09-06-16-31-45.png)
... ...
\ No newline at end of file
PCB-dat/PCB-design-dat/double-side-PCB-dat/double-side-PCB-dat.md
... ...
@@ -1,26 +0,0 @@
1
-
2
-# double-side-PCB-dat
3
-
4
-- [[fab-stencil-double-side]]
5
-
6
-
7
-## General Rules
8
-
9
-| Factor | Rule of Thumb | Reason |
10
-| --------------------------------- | ----------------------------------------------------------------------------- | ---------------------------------------------------------------- |
11
-| **Component size & weight** | **Lighter / smaller SMD components are placed first**, usually on the bottom. | Heavy parts may fall off during second reflow. |
12
-| **Through-hole parts** | Always populated **after reflow** (usually last step). | Reflow ovens are for SMD; THT is wave-soldered or hand-soldered. |
13
-| **BGA, QFN, Fine-pitch ICs** | Usually go on the **primary (top) side**. | Better solder joint reliability and inspection access. |
14
-| **Connectors, mechanical parts** | Preferably on the **primary side**. | Reduces stress during use. |
15
-| **Assembly process optimization** | PCB side with **more components** usually chosen as **first (primary) side**. | Reduces machine setup time and cost. |
16
-
17
-
18
-- [[fab-stencil]]
19
-
20
-
21
-
22
-
23
-
24
-## ref
25
-
26
-- [[double-side-PCB]] - [[PCB-design]]
... ...
\ No newline at end of file
PCB-dat/PCB-design-dat/footprint-dat/2025-05-29-15-10-00.png
... ...
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PCB-dat/PCB-design-dat/footprint-dat/QFN-dat/QFN-dat.md
... ...
@@ -1,47 +0,0 @@
1
-
2
-# QFN-dat
3
-
4
-
5
-## QFN32 table
6
-
7
-| pin | name | note | custom |
8
-| --- | ---- | ---- | ------ |
9
-| 1 | | | |
10
-| 2 | | | |
11
-| 3 | | | |
12
-| 4 | | | |
13
-| 5 | | | |
14
-| 6 | | | |
15
-| 7 | | | |
16
-| 8 | | | |
17
-| 9 | | | |
18
-| 10 | | | |
19
-| 11 | | | |
20
-| 12 | | | |
21
-| 13 | | | |
22
-| 14 | | | |
23
-| 15 | | | |
24
-| 16 | | | |
25
-| 17 | | | |
26
-| 18 | | | |
27
-| 19 | | | |
28
-| 20 | | | |
29
-| 21 | | | |
30
-| 22 | | | |
31
-| 23 | | | |
32
-| 24 | | | |
33
-| 25 | | | |
34
-| 26 | | | |
35
-| 27 | | | |
36
-| 28 | | | |
37
-| 29 | | | |
38
-| 30 | | | |
39
-| 31 | | | |
40
-| 32 | | | |
41
-| pad | | | |
42
-
43
-
44
-
45
-## ref
46
-
47
-- [[footprint-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-design-dat/footprint-dat/SOP8-150-dat/SOP8-150-dat.md
... ...
@@ -1,4 +0,0 @@
1
-
2
-# SOP8-150-dat
3
-
4
-- - width = 3.81 mm = 150 mil
... ...
\ No newline at end of file
PCB-dat/PCB-design-dat/footprint-dat/SOP8-200-dat/2024-08-29-01-56-56.png
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PCB-dat/PCB-design-dat/footprint-dat/SOP8-200-dat/SOP8-200-dat.md
... ...
@@ -1,6 +0,0 @@
1
-
2
-# SOP8-200-dat.md
3
-
4
-- width = 5.08 mm
5
-
6
-![](2024-08-29-01-56-56.png)
... ...
\ No newline at end of file
PCB-dat/PCB-design-dat/footprint-dat/SSOP-dat/2025-09-29-20-25-04.png
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PCB-dat/PCB-design-dat/footprint-dat/SSOP-dat/SSOP-dat.md
... ...
@@ -1,38 +0,0 @@
1
-
2
-# SSOP-dat
3
-
4
-![](2025-09-29-20-25-04.png)
5
-
6
-
7
-
8
-## 0.635 mm Pitch SSOP
9
-- **Pin pitch (e)**: 0.635 mm
10
-- **Lead width (b)**: 0.18 – 0.30 mm
11
-- **Recommended pad width**: ~0.25 mm
12
-- **Recommended pad length**: 1.30 – 1.50 mm
13
-
14
-## 0.65 mm Pitch SSOP
15
-- **Pin pitch (e)**: 0.65 mm
16
-- **Lead width (b)**: 0.22 – 0.38 mm
17
-- **Recommended pad width**: 0.30 mm (nominal)
18
-- **Recommended pad length**: 1.40 – 1.60 mm
19
-- **Pad-to-pad spacing**: 0.35 mm (center-to-center 0.65 mm minus pad width 0.30 mm)
20
-
21
-
22
-## SSOP-16 (0.635 mm pitch) Stop Mask Guidelines
23
-
24
-- **Copper pad width**: ~0.25 mm (typical)
25
-- **Solder mask expansion**: +0.05 – 0.07 mm per side
26
-- **Mask opening width**: ~0.35 – 0.39 mm
27
-- **Pad-to-pad spacing (center-to-center)**: 0.635 mm
28
-- **Mask dam (between pads)**:
29
- - 0.635 – (0.25 + 0.25) – (2 × expansion 0.05–0.07)
30
- - ≈ 0.08 – 0.10 mm left as mask dam
31
-- **Fabrication note**: Some fabs require **≥0.10 mm mask dam**, so if your fab’s capability is 0.10 mm, you are right at the limit.
32
-
33
-
34
-
35
-
36
-## ref
37
-
38
-- [[footprint-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-design-dat/footprint-dat/TQFP-dat/2025-12-12-17-50-40.png
... ...
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PCB-dat/PCB-design-dat/footprint-dat/TQFP-dat/2026-02-20-17-57-23.png
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PCB-dat/PCB-design-dat/footprint-dat/TQFP-dat/2026-02-20-18-03-27.png
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PCB-dat/PCB-design-dat/footprint-dat/TQFP-dat/TQFP-dat.md
... ...
@@ -1,47 +0,0 @@
1
-
2
-# TQFP-dat
3
-
4
-## TQFP32 package
5
-
6
-- [[atmega328-dat]]
7
-
8
-![](2025-12-12-17-50-40.png)
9
-
10
-
11
-## CNV-TQFP32
12
-
13
-![](2026-02-20-17-57-23.png)
14
-
15
- pin 5 = pin 1
16
- pin 6 = pin 2
17
- pin 7 = pin 3
18
- pin 8 = pin 4
19
- pin 9 = pin 5
20
-
21
- pin 22 = pin 18
22
- pin 23 = pin 19
23
- pin 24 = pin 20
24
- pin 25 = pin 21
25
-
26
-
27
-
28
-
29
-
30
-
31
-
32
-
33
-![](2026-02-20-18-03-27.png)
34
-
35
-
36
-
37
-
38
-## ref
39
-
40
-- [[footprint-dat]]
41
-
42
-
43
-
44
-
45
-
46
-
47
-
PCB-dat/PCB-design-dat/footprint-dat/footprint-dat.md
... ...
@@ -1,223 +0,0 @@
1
-
2
-# footprint-dat.md
3
-
4
-- [[EDA-dat]]
5
-
6
-- [[kicad-dat]] - [[kicad-footprint-dat]]
7
-
8
-- [[fab-PCBA-dat]]
9
-
10
-
11
-
12
-## boards
13
-
14
-- [[CCO3628-dat]] - [[CCO3627-dat]]
15
-
16
-- [[DPR1016-dat]]
17
-
18
-- [[CCO3626-dat]] - [[CCO3629-dat]] - [[prog-socket-SMD2DIP-dat]]
19
-
20
-
21
-## footprints
22
-
23
-- [[PLCC-dat]]
24
-
25
-
26
-## pitch large footprint
27
-
28
-- [[SOP-dat]]
29
-
30
-## pitch 0.8mm
31
-
32
-- [[TQFP-dat]]
33
-
34
-## pitch 0.5mm footprint
35
-
36
-- [[QFN-dat]] - [[WLP-dat]] == [[MAX98357-dat]] - [[BQ51050-dat]]
37
-
38
-- [[QFP-dat]]
39
-
40
-- [[SSOP-dat]]
41
-
42
-
43
-
44
-## pitch 0.4mm footprint
45
-
46
-- pitch 0.5mm [[DF40-dat]]
47
-
48
-
49
-
50
-## common footprint libraries
51
-
52
-- [[nettie-dat]]
53
-- [[test-point-dat]]
54
-- Connector_FFC-FPC
55
-- Connector_PinHeader_1.00mm
56
-- Connector_PinSocket_1.00mm
57
-- Connector_JST
58
-- Connector_Molex
59
-- Jumper
60
-- Connector_Wire
61
-- Package_CSP
62
-
63
-
64
-## IC Package Footprintscategorized by pitch
65
-
66
-
67
-| Pitch (mm) | Package Types & Examples |
68
-|------------|-------------------------------------------------------------------------------------------|
69
-| **0.3 mm** | WLCSP (Wafer Level Chip Scale Package), uBGA (Ultra Fine Pitch BGA), QFN (fine pitch) |
70
-| **0.35 mm**| DFN (small pitch variants), QFN (ultra fine pitch), LGA |
71
-| **0.4 mm** | QFN (fine pitch), CSP (Chip Scale Package), BGA (fine pitch), DFN |
72
-| **0.5 mm** | QFN (common pitch), TQFP (fine pitch), LGA, DFN |
73
-| **0.635 mm** | SSOP (Shrink Small Outline Package), TSSOP (Thin Shrink SOP) |
74
-| **0.8 mm** | QFP (Quad Flat Package), TQFP (standard pitch), LQFP, BGA (medium pitch) |
75
-| **1.0 mm** | QFP (larger pitch), LQFP, PLCC (Plastic Leaded Chip Carrier), SOIC (narrow pitch) |
76
-| **1.27 mm**| SOIC (Small Outline IC), DIP (Dual In-line Package), PLCC |
77
-| **1.5 mm** | Older DIP variants, larger SIP (Single In-line Package) |
78
-| **2.0 mm** | Some DIP, SIP, Power Packages (TO-220 multi-pin) |
79
-| **2.54 mm (0.1")** | Standard DIP (most common), SIP, headers, through-hole connectors |
80
-
81
-
82
-## Methods to Examine Hidden Solder Bridges Under Packages
83
-
84
-| Method | Description | Pros | Cons / Limitations |
85
-|--------------------------------|-----------------------------------------------------------------------------|------------------------------------------|-----------------------------------------|
86
-| **X-Ray Inspection** | Uses 2D or 3D X-ray (AXI/CT) to image solder joints under the package. | Most reliable, can see voids, bridges, opens | Expensive equipment, not DIY friendly |
87
-| **Microscope with Oblique Light** | Tilted inspection around chip edges, sometimes you can see solder "squeeze-out". | Cheap, immediate check | Only shows gross defects near edges |
88
-| **Electrical Continuity Test** | Use multimeter to check resistance between adjacent pins/pads. | Simple, effective for shorts | Cannot detect open joints or cold solder|
89
-| **Boundary Scan (JTAG)** | IC self-tests connectivity if supported. | Automated, precise | Only available if IC has JTAG support |
90
-| **Thermal Camera / IR Imaging**| Power up board, shorts often cause local hot spots. | Non-contact, quick check | Needs power-on, risk of damage |
91
-| **Flying Probe / ICT Test** | Automated test system probes nets for shorts/opens. | Precise, production use | Expensive, setup time |
92
-| **Acoustic Microscopy (SAM)** | Ultrasound imaging can detect voids or poor solder bonding. | High resolution for reliability testing | Very expensive, lab equipment only |
93
-
94
-
95
-For hobbyist / small-lab use:
96
-
97
-**Best option**: Electrical continuity check with a **multimeter** (between power rails, adjacent pins).
98
-
99
-Second best: If you suspect hidden bridges, try **thermal camera** (small USB IR cameras are affordable).
100
-
101
-Pro-level: Use an **X-ray machine** (common in professional PCB assembly houses).
102
-
103
-👉 If you’re debugging **why the IC doesn’t work after reflow**, I’d suggest:
104
-
105
-Check for shorts with multimeter.
106
-
107
-Power briefly, then feel for **overheating** (carefully) or use thermal camera.
108
-
109
-If nothing obvious, suspect **opens (unsoldered pads)**, which can only be 100% confirmed by X-ray or functional testing.
110
-
111
-
112
-
113
-## DIY Methods to Detect Hidden Solder Bridges Under Packages (No X-Ray)
114
-
115
-| Method | How It Works | Notes / Tips |
116
-|--------------------------------|-------------------------------------------------------------------------------|--------------|
117
-| **Multimeter Continuity Check**| With power off, measure resistance between power rails (VCC–GND) and between suspect pins. | If you read ~0Ω or very low resistance, there may be a bridge. |
118
-| **Current-Limited Power Test** | Power board with a bench supply set to current limit (e.g. 50–100mA). If supply immediately hits limit, there’s likely a short. | Use low limit to avoid chip damage. |
119
-| **Thermal Finger Test / IR Camera** | Briefly power on with current limit. A solder bridge often causes a tiny hot spot. | Safer with cheap USB thermal cameras. |
120
-| **Rosin / Alcohol Wetting** | Apply isopropyl alcohol or rosin flux around package edges, then power board. If there is a short, liquid may boil or show bubbles near bridged pads. | Not very precise, but sometimes works. |
121
-| **Resistance Mapping** | Compare resistance between ground and each I/O pin versus a known-good board. | Detects anomalies indirectly. |
122
-| **Functional "Wiggle Test"** | Gently press down or heat package with hot air. If circuit suddenly works or fails, some pads may be bridged or floating. | Risky — only use for debugging prototypes. |
123
-
124
-Practical DIY Workflow
125
-
126
-**First step**: Check resistance between **VCC and GND** before powering. If it’s suspiciously low, suspect a bridge.
127
-
128
-**Second step**: Use **current-limited bench supply** to power on — check for overheating.
129
-
130
-**Third step**: If possible, use **cheap thermal camera** (even phone add-ons) to find hot spots.
131
-
132
-**Last resort**: Rework package with **flux + hot air and reflow** — often fixes hidden bridges without even finding them.
133
-
134
-👉 This way you don’t need expensive X-ray, just a multimeter, alcohol/flux, and maybe a thermal camera.
135
-
136
-
137
-
138
-## general footprint guide
139
-
140
-### overal setup
141
-
142
-| Setting | 1 | 2 | 3 | 4 |
143
-| ------------- | --- | ---- | ----- | -------- |
144
-| Grid Size | 1.0 | 0.5 | 1.27 | 2.54 mm |
145
-| Snap Size | 0.1 | 0.05 | 0.127 | 0.254 mm |
146
-| Alt Snap Size | 0.1 | 0.05 | 0.127 | 0.254 mm |
147
-
148
-
149
-- units == mm
150
-
151
-### create new footprint
152
-
153
-- pad
154
-- layer select
155
- - for SMD part == top / bottom layer only
156
- - for THT part == all layer
157
- - also check the hole size and shape
158
-
159
-
160
-
161
-## generate footprint descriptions
162
-
163
-CAP 4.7UF, 0805, 10%, MLCC, 50V, X5R, ROHS
164
-
165
-RES 1K 5%, 0805, THICK FILM, 150V, 1/8W, ROHS
166
-
167
-Here's a breakdown of the structure:
168
-
169
-- CAP/RES: Component Type (Capacitor or Resistor)
170
-- 4.7UF/1K: Value (4.7 Microfarads or 1 Kiloohm)
171
-- 0805: Package Size (0805 is a standard SMD package size)
172
-- 10%/5%: Tolerance (10% or 5% variation in value)
173
-- MLCC/THICK FILM: Technology or Type (Multi-Layer Ceramic Capacitor or Thick Film Resistor)
174
-- 50V/150V: Voltage Rating (50 Volts or 150 Volts)
175
-- X5R: Dielectric (Specific to capacitors, defines temperature characteristics)
176
-- 1/8W: Power Rating (1/8 Watt, specific to resistors)
177
-- ROHS: RoHS Compliant (Restriction of Hazardous Substances)
178
-
179
-LED SMD VERMELHO, 0805, 2V, 25MA, 624NM, 60MCD, 140°, ROHS
180
-
181
-- "VERMELHO" is Portuguese for red.
182
-- 624nm wavelength corresponds to red light on the visible spectrum.
183
-- Other details like 2V, 25mA, and 60mcd just describe electrical and luminous specs.
184
-
185
-
186
-
187
-
188
-
189
-
190
-
191
-
192
-### Electronic Industries Alliance (EIA)
193
-
194
-
195
-EIA 3528-21 Meaning
196
-
197
-| Section | Description |
198
-| ------- | --------------------------------------------------------------------------------------------------------------- |
199
-| 3528 | Physical size of the component in hundredths of inches: 3.5 mm x 2.8 mm (i.e., 0.138" x 0.110") |
200
-| -21 | Indicates a specific height and pad layout variation within the 3528 size range. Typically means ~2.1 mm height |
201
-
202
-
203
-CRISTAL 12MHz, SMD, 3.2X2.5MM, 18PF, 20PPM, ROHS
204
-
205
-This corresponds to the standard 3225 SMD package (also known as EIA 3225 or 3.2x2.5mm SMD crystal).
206
-
207
-## SOD-123
208
-
209
-SOD-123 is a small SMD package used for diodes, transistors, and other components. It has a footprint of approximately 1.6mm x 0.8mm (0.063" x 0.031") and is commonly used in low-power applications.
210
-
211
-![](2025-05-29-15-10-00.png)
212
-
213
-
214
-
215
-## SOD-323
216
-
217
-
218
-
219
-## ref
220
-
221
-- [[BOM-dat]]
222
-
223
-- [[kicad-pcb-dat]]
... ...
\ No newline at end of file
PCB-dat/PCB-design-dat/footprint-dat/nettie-dat/2025-09-06-16-31-45.png
... ...
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PCB-dat/PCB-design-dat/footprint-dat/nettie-dat/nettie-dat.md
... ...
@@ -1,6 +0,0 @@
1
-
2
-# nettie-dat
3
-
4
-[[kicad-dat]] - nettie
5
-
6
-![](2025-09-06-16-31-45.png)
... ...
\ No newline at end of file
projects-dat/projects-dat.md
... ...
@@ -0,0 +1,9 @@
1
+
2
+
3
+# projects-dat.md
4
+
5
+fun / learnable / popular projects, sort by date
6
+
7
+- esp-drone - https://github.com/Circuit-Digest/ESP-Drone
8
+
9
+